KR930011499B1 - Isolation method of semiconductor - Google Patents

Isolation method of semiconductor Download PDF

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KR930011499B1
KR930011499B1 KR1019910000568A KR910000568A KR930011499B1 KR 930011499 B1 KR930011499 B1 KR 930011499B1 KR 1019910000568 A KR1019910000568 A KR 1019910000568A KR 910000568 A KR910000568 A KR 910000568A KR 930011499 B1 KR930011499 B1 KR 930011499B1
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impurity
semiconductor substrate
semiconductor
substrate
oxide film
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KR1019910000568A
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KR920015507A (en
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양두영
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The isolating device of a semiconductor device is isolated by implanting nitrogen as impurity into a semiconductor substrate, heat-treating the implanted impurity to form an impurity layer, selectively etching the substrate in the vertical direction with the impurity layer used as etch-stopper, coating a CVD oxide film on all the area of the substrate, etch-backing to reflow, grinding the surface. The vertical etching prevents production of any unnecessary area.

Description

반도체장치의 소자격리방법Device isolation method of semiconductor device

제1도는 종래의 소자격리된 반도체장치의 구조도.1 is a structural diagram of a conventional device isolated semiconductor device.

제2a도~제2e도는 본 발명의 1실시예에 따른 제조공정도.2a to 2e is a manufacturing process diagram according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체기판 12 : 질화층11 semiconductor substrate 12 nitride layer

13 : CVD 산화막13: CVD oxide film

본 발명은 반도체장치의 제조공정에 관한 것으로, 특히 액티브영역의 유효부분축소를 방지하여 고집적 메모리 소자에 적용하도록 한 반도체장치의 소작격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method for small isolation of a semiconductor device, which is applied to a highly integrated memory device by preventing effective partial reduction of an active region.

종래에는, 제1도에 도시한 바와 같이 반도체기판(1)상에 질화막과 포토레지스트(도시하지 않음)를 이용하여 채널스톱을 위한 불순물주입 및 필드영역에 필드산화막(2)을 형성으로 반도체장치의 소작격리를 행하였다. 즉, 액티브영역간의 주화(Crosstalk)가 발생되지 않도록 필드산화막(2)과 채널스토퍼를 형성하였다.Conventionally, as shown in FIG. 1, a semiconductor device is formed by implanting impurity for channel stop and forming a field oxide film 2 in a field region using a nitride film and a photoresist (not shown) on the semiconductor substrate 1 as shown in FIG. Cauterization of was performed. In other words, the field oxide film 2 and the channel stopper are formed so that crosstalk between the active regions does not occur.

그러나, 이러한 종래기술은 정션에 의한 넓은 공핍층으로 인하여 누설전류의 발생확률이 높으며, 또한 액티브영역으로 침투되는 버드 비크(Bird's Beak)형상의 발생으로 고집적화에 많은 장해 요소가 되고 있다.However, such a prior art has a high probability of occurrence of leakage current due to the wide depletion layer by the junction, and also causes many obstacles for high integration due to the generation of a bird's beak shape penetrating into the active region.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 액티브 영역을 절연체막으로 둘러싼 반도체장치의 소자격리방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a device isolation method for a semiconductor device in which an active region is surrounded by an insulator film.

이와 같은 목적을 달성하기 위한 본 발명의 특징은 반도체기판내부에 불순물을 이온주입하는 공정과, 이온주입된 불순물로 된 불순물층을 형성하도록 열처리하는 공정과, 불순물층을 에치스토퍼로 사용하여 반도체기판을 수직방향으로 선택적 식각하는 공정과, 전면에 CVD 산화막을 도포하고 에치백하여 평탄화하는 공정과, 표면을 그라인딩시키는 공정으로 이루어진 반도체장치의 소자격리방법에 있다.Features of the present invention for achieving the above object are a step of ion implanting impurities into a semiconductor substrate, a step of heat treatment to form an impurity layer of ion implanted impurities, and a semiconductor substrate using an impurity layer as an etch stopper. Is a method of isolating a semiconductor device in a vertical direction, applying a CVD oxide film to the entire surface, etching back to planarize, and grinding the surface.

이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.

제2a도~제2e도는 본 발명의 1실시예에 따른 제조공정도로서, 우선 제2a도에 도시한 바와 같이 불순물 예를들어, 질소를 반도체기판(11) 내부의 원하는 깊이만큼 침투하도록 도즈량 및 에너지를 조절하여 이온주입한 후, 제2b도와 같이 열처리하여 반도체기판(11) 내부에 이온주입된 질소를 질화시켜 질화층(12)을 형성시킨다. 이때, 이온주입에 의한 손상도 재결정으로 회복된다.2a to 2e are manufacturing process diagrams according to one embodiment of the present invention. First, as shown in FIG. 2a, the dose and energy of impurities such as nitrogen to penetrate to a desired depth inside the semiconductor substrate 11 are shown. After controlling the ion implantation, heat treatment is performed as shown in FIG. 2b to nitride the nitrogen implanted into the semiconductor substrate 11 to form the nitride layer 12. At this time, damage by ion implantation is also recovered to recrystallization.

그후, 제2c도와 같이 질화층(12)을 에치스토퍼(Stopper)로 사용하여 반도체기판(11)을 수직방향으로 선택적 에칭한 다음, 제2d도와 같이 CVD(Chemical Vapour Deposition)산화막(13)을 도포하고 에치백하여 평탄화한 다음, 기계적으로 그라인딩(Grinding)시키면 제2e도와 같이 수직적으로 정의되고 평탄화된 반도체장치의 소자격리를 이룰 수 있게 된다.Thereafter, the semiconductor substrate 11 is selectively etched in the vertical direction using the nitride layer 12 as an etch stopper as shown in FIG. If the substrate is etched back and planarized, and then mechanically grinding, the isolation of the semiconductor device can be achieved.

여기서, CVD산화막(12)의 도포 및 에치백을 반복수행하여 CVD산화막(12)의 프로파일(Profile)을 개선시킬 수도 있다.Here, the coating and etch back of the CVD oxide film 12 may be repeatedly performed to improve the profile of the CVD oxide film 12.

이상 설명한 바와 같이, 본 발명에 따르면 수직식각을 실행하여 반도체장치의 소자격리를 하게 되므로 불필요한 영역이 발생되지 않게 되어 고집적화에 유리한 이점에 있으며, 또한 액티브영역의 5면을 절연체층으로 둘러싸게 되므로 누설전류 및 누화에 대한 우려를 현저히 감소시킬 수 있는 효과가 있다.As described above, according to the present invention, since the device is isolated from the semiconductor device by performing vertical etching, unnecessary areas are not generated, which is advantageous in terms of high integration, and since five surfaces of the active area are surrounded by an insulator layer, leakage occurs. There is an effect that can significantly reduce the concern about current and crosstalk.

Claims (2)

반도체기판 내부에 불순물을 이온주입하는 공정과, 상기 이온주입된 불순물로 된 불순물층을 형성하도록 열처리하는 공정과, 상기 불순물층을 에치스토퍼로 사용하여 상기 반도체기판을 수직방향으로 선택적 식각하는 공정과, 전면에 CVD 산화막을 도포하고 에치백하여 평탄화하는 공정과, 표면을 그라인딩시키는 공정으로 이루어진 반도체장치의 소자격리방법.Ion implanting impurities into the semiconductor substrate, heat treatment to form an impurity layer of the ion implanted impurities, and selectively etching the semiconductor substrate vertically using the impurity layer as an etch stopper; And a step of applying a CVD oxide film to the entire surface, etching back to planarize, and grinding the surface. 제1항에 있어서, 상기 이온주입된 불순물은 질소인 것을 특징으로 하는 반도체장치의 소자격리방법.The device isolation method of claim 1, wherein the ion implanted impurity is nitrogen.
KR1019910000568A 1991-01-15 1991-01-15 Isolation method of semiconductor KR930011499B1 (en)

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