KR930011421A - 스큐를 최소로한 다중클록 수신기용 고속클록회로 - Google Patents

스큐를 최소로한 다중클록 수신기용 고속클록회로 Download PDF

Info

Publication number
KR930011421A
KR930011421A KR1019920021739A KR920021739A KR930011421A KR 930011421 A KR930011421 A KR 930011421A KR 1019920021739 A KR1019920021739 A KR 1019920021739A KR 920021739 A KR920021739 A KR 920021739A KR 930011421 A KR930011421 A KR 930011421A
Authority
KR
South Korea
Prior art keywords
signal
clock
output
input
driving means
Prior art date
Application number
KR1019920021739A
Other languages
English (en)
Korean (ko)
Inventor
테스타 제임스
Original Assignee
마이클 에이치. 모리스
선 마이크로시스템즈 인코오퍼레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마이클 에이치. 모리스, 선 마이크로시스템즈 인코오퍼레이티드 filed Critical 마이클 에이치. 모리스
Publication of KR930011421A publication Critical patent/KR930011421A/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dram (AREA)
KR1019920021739A 1991-11-21 1992-11-19 스큐를 최소로한 다중클록 수신기용 고속클록회로 KR930011421A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79553891A 1991-11-21 1991-11-21
US795,538 1991-11-21

Publications (1)

Publication Number Publication Date
KR930011421A true KR930011421A (ko) 1993-06-24

Family

ID=25165775

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920021739A KR930011421A (ko) 1991-11-21 1992-11-19 스큐를 최소로한 다중클록 수신기용 고속클록회로

Country Status (3)

Country Link
EP (1) EP0543542A2 (US20100056889A1-20100304-C00004.png)
JP (1) JPH05241676A (US20100056889A1-20100304-C00004.png)
KR (1) KR930011421A (US20100056889A1-20100304-C00004.png)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02187811A (ja) * 1989-01-13 1990-07-24 Mitsubishi Electric Corp クロックジェネレータ

Also Published As

Publication number Publication date
JPH05241676A (ja) 1993-09-21
EP0543542A2 (en) 1993-05-26
EP0543542A3 (US20100056889A1-20100304-C00004.png) 1994-08-31

Similar Documents

Publication Publication Date Title
US5452436A (en) System for connecting plurality of electronic units to data and clock buses wherein transmitting and receiving data in synchronization with transmitting and receiving clock signals
KR910010529A (ko) 시프트 레지스터 장치
US5706484A (en) Method for eliminating transition direction sensitive timing skews in a source synchronous design
US4645947A (en) Clock driver circuit
ATE381051T1 (de) Verfahren und vorrichtung zur kopplung von signalen zwischen zwei schaltungen, in verschiedenen taktbereichen arbeitend
KR900014970A (ko) 동기 회로
SE8604262L (sv) Databehandlingsanordning bestaende av ett flertal parallellarbetande databehandlingsmoduler, multipel redundant klockanordning med ett antal inbordes sjelvsynkroniserande klockkretsar avsedd att anvendas i en sadan data
KR920704428A (ko) 고속 프리스케일러
US6507230B1 (en) Clock generator having a deskewer
JPS5921045B2 (ja) クロツク信号分配回路の調整方式
US5249214A (en) Low skew CMOS clock divider
KR930011421A (ko) 스큐를 최소로한 다중클록 수신기용 고속클록회로
US4056736A (en) Injection logic arrangements
KR910007266A (ko) 클럭 및 제어 신호 발생 회로
KR100249019B1 (ko) 주파수 분주회로
JPH04233014A (ja) コンピュータ・システム
KR960012943A (ko) 동기 회로
KR200296046Y1 (ko) 주파수분주장치
SU1483631A2 (ru) Делитель частоты с трехфазным выходом
SU544111A1 (ru) Формирователь импульсов
KR0184153B1 (ko) 주파수 분주 회로
KR960001156B1 (ko) 클럭신호 전송회로
SU613493A1 (ru) Формирователь одиночных импульсов
KR880014756A (ko) 시분할 다중통신 시스템에 있어서 동기신호 발생 및 자국 및 타국 데이타의 결합회로
KR930011666A (ko) 전하 결합소자(ccd)구동 ic 회로

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application