KR930010941A - Error correction circuit of digital signal - Google Patents

Error correction circuit of digital signal Download PDF

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Publication number
KR930010941A
KR930010941A KR1019910019979A KR910019979A KR930010941A KR 930010941 A KR930010941 A KR 930010941A KR 1019910019979 A KR1019910019979 A KR 1019910019979A KR 910019979 A KR910019979 A KR 910019979A KR 930010941 A KR930010941 A KR 930010941A
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KR
South Korea
Prior art keywords
error
signal
error correction
unit
flag
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Application number
KR1019910019979A
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Korean (ko)
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KR940000681B1 (en
Inventor
박종엽
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이헌조
주식회사 금성사
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Priority to KR1019910019979A priority Critical patent/KR940000681B1/en
Publication of KR930010941A publication Critical patent/KR930010941A/en
Application granted granted Critical
Publication of KR940000681B1 publication Critical patent/KR940000681B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1816—Testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1816—Testing
    • G11B2020/1823—Testing wherein a flag is set when errors are detected or qualified

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음No content

Description

디지탈 신호의 에러 정정회로Error correction circuit of digital signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 디지탈 신호 기록/재생 시스템의 블록도.1 is a block diagram of a general digital signal recording / reproducing system.

제2도는 본 발명 디지탈 신호의 에러 정정 회로가 적용되는 디지탈 신호 처리 블록도.2 is a digital signal processing block diagram to which the error correction circuit of the present invention digital signal is applied.

제3도는 제2도에서 에러 판별 및 에러 플래그 발생부의 일실시 예시회로도.3 is an exemplary circuit diagram of an error discrimination and error flag generator in FIG. 2;

제4도의 (a) 내지 (f)는 제3도 각부의 파형도.(A)-(f) of FIG. 4 are the waveform diagrams of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 기록 매체 20 : 신호 검출부10: recording medium 20: signal detection unit

30 : 복조부 40 : 에러 정정 및 복호부30: demodulation unit 40: error correction and decoding unit

50 : 에러 판별 및 에러 플래그발생부 51 : 에러 판별부50: error determination and error flag generation unit 51: error determination unit

52 : 에러 플래그 발생부 52A : 펄스폭 변환부52: error flag generator 52A: pulse width converter

52B : 카운터 AD1 : 앤드 게이트52B: Counter AD1: End Gate

OR11 : 오아 게이트 FF1-FF4, FF11-FF2l : 플립플롭OR11: ora gate FF1-FF4, FF11-FF2l: flip-flop

Claims (2)

기록 매체(10)에 기록된 데이타를 신호 검출부(20), 복조부(30), 에러 정정 및 복호부(40)를 통해 검출해내는 디지탈 신호 처리 시스템에 있어서, 상기 신호 검출부(20)의 출력신호를 공급받아 소정 비트를 단위로 하여 연속되는 동일 데이타 값(0 또는 1)이 검출될때 에러 검출신호(ED)를 발생하고, 상기 신호 검출부(20)에서 검출된 동기신호(SYNC)와 그 에러 검출신호(ED)를 공급받아 에러가 위치하는 지점에서 에러플래그(EF)를 발생하여 이를 상기 에러 정정 및 복호부(40)에 출력하는 에러 판별 및 에러 플래그 발생부(50)를 포함하여 구성한 것을 특징으로 하는 디지탈 신호의 에러 정정 회로.In the digital signal processing system for detecting data recorded on the recording medium 10 through the signal detector 20, the demodulator 30, the error correction and the decoder 40, the output of the signal detector 20 When the same data value (0 or 1) is detected by receiving a signal in units of predetermined bits, an error detection signal ED is generated, and the synchronization signal SYNC detected by the signal detection unit 20 and its error are detected. And an error discrimination and error flag generator 50 for generating an error flag EF at the point where the error is located by receiving the detection signal ED and outputting the error flag EF to the error correction and decoding unit 40. An error correction circuit for a digital signal characterized by the above-mentioned. 제 1항에 있어서, 상기 에러판별 및 에러플래그 발생부(50)를 상기 신호 검출부(20)로부터 공급되는 디지탈 데이타(DIN) 및 클럭신호(CK)를 공급받아 시프트시킨 소정 비트구간의 데이타 값이 모두 동일 값일때 에러 검출신호(ED)를 발생하는 에러 판별부(51)와, 상기 에러 판별부(51)로부터 에러 검출신호(ED)가 공급될때 심볼 단위로 펄스폭을 변환하는 펄스폭 변환부(52A)와, 클럭신호(CK) 및 동기 신호(SYNC)를 공급받아 심볼주기의 반주기마다 반전되는 펄스를 출력하는 카운터(52B)와, 상기 카운터(52B)의 출력신호를 클럭신호로 공급받고, 상기 펄스폭 변환부(52A)의 출력신호를 입력데이타로 하여 에러 정정 플래그(EF)를 생성하는 플립플롭(FF21)로 구성한 것을 특징으로 하는 디지탈 신호의 에러 정정회로.The data value of a predetermined bit section according to claim 1, wherein the error discrimination and error flag generator (50) is shifted by receiving the digital data (D IN ) and the clock signal (CK) supplied from the signal detector (20). An error discriminating unit 51 for generating an error detection signal ED when the values are the same, and a pulse width conversion for converting a pulse width in symbol units when the error detecting signal ED is supplied from the error discriminating unit 51. A counter 52B which receives the unit 52A, the clock signal CK and the synchronization signal SYNC, and outputs a pulse inverted every half of the symbol period, and supplies the output signal of the counter 52B as a clock signal. And a flip-flop (FF21) for generating an error correction flag (EF) using the output signal of the pulse width converter (52A) as input data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910019979A 1991-11-11 1991-11-11 Digital signal error correcting circuit KR940000681B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019979A KR940000681B1 (en) 1991-11-11 1991-11-11 Digital signal error correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019979A KR940000681B1 (en) 1991-11-11 1991-11-11 Digital signal error correcting circuit

Publications (2)

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KR930010941A true KR930010941A (en) 1993-06-23
KR940000681B1 KR940000681B1 (en) 1994-01-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905667A (en) * 1995-12-30 1999-05-18 Hyundai Electronics Industries Co., Ltd. Full adder using NMOS transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905667A (en) * 1995-12-30 1999-05-18 Hyundai Electronics Industries Co., Ltd. Full adder using NMOS transistor

Also Published As

Publication number Publication date
KR940000681B1 (en) 1994-01-27

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