KR930010673A - Level Detector Control Circuit for Vpp Generator - Google Patents

Level Detector Control Circuit for Vpp Generator Download PDF

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Publication number
KR930010673A
KR930010673A KR1019910021020A KR910021020A KR930010673A KR 930010673 A KR930010673 A KR 930010673A KR 1019910021020 A KR1019910021020 A KR 1019910021020A KR 910021020 A KR910021020 A KR 910021020A KR 930010673 A KR930010673 A KR 930010673A
Authority
KR
South Korea
Prior art keywords
level detector
vpp generator
vpp
control circuit
mosfet
Prior art date
Application number
KR1019910021020A
Other languages
Korean (ko)
Other versions
KR940003125B1 (en
Inventor
김홍석
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910021020A priority Critical patent/KR940003125B1/en
Publication of KR930010673A publication Critical patent/KR930010673A/en
Application granted granted Critical
Publication of KR940003125B1 publication Critical patent/KR940003125B1/en

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)

Abstract

본 발명은 Vpp발생기용 레벨 디텍터 제어회로에 관한 기술로, 한개의 레벨디텍터로서 2개의 Vpp펌프회로를 제어할 수 있으며, 액티브 및 스탠바이 상태를 DRAM의 내부제어신호를 사용, 제어하여 불필요한 전류가 차단되도록 한 기술이다.The present invention relates to a level detector control circuit for a Vpp generator, which can control two Vpp pump circuits as one level detector, and blocks unnecessary current by controlling active and standby states using an internal control signal of a DRAM. It is a technique that is possible.

Description

Vpp 발생기용 레벨 디텍터 제어회로Level Detector Control Circuit for Vpp Generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a 및 2b도는 제1도의 동작설명을 위한 파형도.2A and 2B are waveform diagrams for explaining the operation of FIG.

제3도는 본 발명에 따른 레벨디텍터의 상세회로도.3 is a detailed circuit diagram of a level detector according to the present invention.

제4도는 본 발명의 실시예도.4 is an embodiment of the present invention.

Claims (2)

레벨디텍터(1 또는 2), 링오실레이타(3 또는 4) 및 Vpp 펌프(5 또는 6)로 구성되는 Vpp 발생기에 있어서, 상기 레벨디텍터(1 또는 2)의 한단자는 MOSFET N1을 통해 저지되고, 상기 레벨디텍터(1 또는 2)의 다른 단자는 MOSFET P1을 경유해 접지되며, 제어신호 φRDE, φOE 및 φCBR을 입력으로하는 오아게이트 G4의 출력단자는 상기 MOSFET N1의 게이트 단자와 접속된채로 반전게이트 G5를 경유해 상기 MOSFET P1의 게이트 단자에 접속구성되는 것을 특징으로 하는 Vpp 발생기용 레벨디텍터 제어회로.In a Vpp generator consisting of a level detector (1 or 2), a ring oscillator (3 or 4) and a Vpp pump (5 or 6), one terminal of the level detector (1 or 2) is interrupted via MOSFET N1. The other terminal of the level detector 1 or 2 is grounded through the MOSFET P1, and the output terminal of the OR gate G4 which inputs the control signals φRDE, φOE and φ CBR is connected to the gate terminal of the MOSFET N1, and is inverted. A level detector control circuit for a Vpp generator, which is connected to a gate terminal of the MOSFET P1 via G5. 2개의 레벨디텍터를 구비한 Vpp 발생기에 있어서, 한개의 레벨디텍터는 제어신호 φRDE 및 φOE를 입력으로 하는 오아게이트 G7의 출력을 입력으로 하고, 다른 한개의 레벨디텍터는 제어신호 φCBR을 입력으로 하도록 구성되는 것을 특징으로 하는 Vpp 발생기.In the Vpp generator with two level detectors, one level detector is configured to input the output of the OAGATE G7 with the control signals φRDE and φOE as input, and the other level detector as the input of the control signal φCBR. Vpp generator, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910021020A 1991-11-23 1991-11-23 Level detector control circuit for vpp generator KR940003125B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910021020A KR940003125B1 (en) 1991-11-23 1991-11-23 Level detector control circuit for vpp generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910021020A KR940003125B1 (en) 1991-11-23 1991-11-23 Level detector control circuit for vpp generator

Publications (2)

Publication Number Publication Date
KR930010673A true KR930010673A (en) 1993-06-23
KR940003125B1 KR940003125B1 (en) 1994-04-13

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ID=19323361

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910021020A KR940003125B1 (en) 1991-11-23 1991-11-23 Level detector control circuit for vpp generator

Country Status (1)

Country Link
KR (1) KR940003125B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686259B2 (en) 2001-03-09 2004-02-03 Samsung Electronics Co., Ltd. Method for manufacturing solid state image pick-up device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686259B2 (en) 2001-03-09 2004-02-03 Samsung Electronics Co., Ltd. Method for manufacturing solid state image pick-up device

Also Published As

Publication number Publication date
KR940003125B1 (en) 1994-04-13

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