KR930009110A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR930009110A
KR930009110A KR1019910018041A KR910018041A KR930009110A KR 930009110 A KR930009110 A KR 930009110A KR 1019910018041 A KR1019910018041 A KR 1019910018041A KR 910018041 A KR910018041 A KR 910018041A KR 930009110 A KR930009110 A KR 930009110A
Authority
KR
South Korea
Prior art keywords
base
manufacturing
oxide film
diffusion layer
field oxide
Prior art date
Application number
KR1019910018041A
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Korean (ko)
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KR940007454B1 (en
Inventor
민성기
김동준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910018041A priority Critical patent/KR940007454B1/en
Publication of KR930009110A publication Critical patent/KR930009110A/en
Application granted granted Critical
Publication of KR940007454B1 publication Critical patent/KR940007454B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 바이폴라 트랜지스터의 제조방법에 관한 것으로, 반도체 기판상에 베이스영역 형성공정중에서 능동소자 절연을 위한 필드산화막을 형성하기 전에 포토마스크를 사용하여 베이스확산층 가장자리의 필드산화막을 형성하기 전에 포토마스크를 사용하여 베이스확산층 가장자리의 필드산화막 아래에 일정한 거리를 두고 베이스와 같은 도전형의 물질을 이온주입하여 베이스접합의 곡률을 키워주는 p형 확산층을 형성함으로써 항복전압을 개성한 바아폴라 트랜지스터의 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor, wherein a photomask is formed before forming a field oxide film at the edge of the base diffusion layer using a photomask before forming a field oxide film for active device isolation during a base region formation process on a semiconductor substrate. Is a method of manufacturing a Bapolar transistor with individual breakdown voltage by forming a p-type diffusion layer which increases the curvature of the base junction by ion implanting a conductive material such as a base at a distance below the field oxide film at the edge of the base diffusion layer. .

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)-(f)는 본 발명에 따른 바이폴라 트랜지스터의 제조공정을 나타내는 단면도.1 (a)-(f) are sectional views showing the manufacturing process of a bipolar transistor according to the present invention.

Claims (2)

반도체기판(1)상의 고불순물 농도의 n형 및 p형 매몰층(2, 10)과 이 매몰층 상부에 저불순물 농도로 형성된 n웰(2)과 p웰 이루어진 바이폴라 트랜지스터의 제조방법에 있어서, 능동소자 절연을 위한 필드산화막(9)을 형성하기 전에 포토마스크를 로사용하여 베이스 확산층(13) 가장자리의 필드산화막 아래에 일정한 거리를 두고 베이스와 같은 도전형의 물질을 이온주입하여 베이스접합의 곡률을 키워주는 p형 확산층(8)을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.In the method of manufacturing a bipolar transistor comprising n-type and p-type buried layers (2, 10) of high impurity concentration on semiconductor substrate (1) and n-well (2) and p-well formed at low impurity concentration on the buried layer, Before forming the field oxide film 9 for the isolation of active devices, a curvature of the base junction is formed by ion implanting a conductive material such as a base at a predetermined distance below the field oxide film at the edge of the base diffusion layer 13 using a photomask. A method of manufacturing a semiconductor device, characterized by forming a growing p-type diffusion layer (8). 제1항에 있어서, 상기 베이스영역의 곡률을 키워지는 활성층(8)을 형성하기 위해 불순물은 붕소(B), 도우즈 1E13-14ion/㎠에너지 30-80KeV 상태로 주입하는 것을 특징으로 하는 반도체장치의 제조방법.The semiconductor device according to claim 1, wherein the impurity is implanted in a state of boron (B) and dose 1E13-14ion / cm 2 energy of 30-80 KeV to form the active layer 8 which increases curvature of the base region. Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910018041A 1991-10-14 1991-10-14 Manufacturing method of semiconductor device KR940007454B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910018041A KR940007454B1 (en) 1991-10-14 1991-10-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018041A KR940007454B1 (en) 1991-10-14 1991-10-14 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR930009110A true KR930009110A (en) 1993-05-22
KR940007454B1 KR940007454B1 (en) 1994-08-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018041A KR940007454B1 (en) 1991-10-14 1991-10-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR940007454B1 (en)

Also Published As

Publication number Publication date
KR940007454B1 (en) 1994-08-18

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