KR930009071B1 - Semiconductor memory device installed driving line of sense amplifier in sense amp and memory cell - Google Patents

Abstract

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Description

Miniaturized semiconductor memory device with sensing amplifier drive line installed on sensing amplifier and memory cell

1 is a circuit diagram illustrating an example of a conventional semiconductor memory device.

2 is an opening diagram for explaining a problem of the conventional semiconductor memory device.

3 is a principle diagram showing a first embodiment of a semiconductor memory device of the present invention.

4 is a circuit diagram showing a first embodiment of the semiconductor memory device of the present invention.

5 is a circuit diagram showing a modification of the first embodiment of the semiconductor memory device of the present invention.

Fig. 6 is an opening diagram showing the arrangement of memory cell blocks and sense amplifiers in a DRAM device.

7 is a principle diagram showing a second embodiment of the semiconductor memory device of the present invention.

8 is a circuit diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 9 is an opening circuit diagram showing a part of the semiconductor memory device shown in FIG.

10 is a circuit diagram showing a third embodiment of the semiconductor memory device of the present invention.

11 is a partial cross-sectional view of the semiconductor memory device shown in FIG.

12 is a partial circuit diagram of the semiconductor memory device shown in FIG.

Fig. 13 is an opening circuit diagram showing a third embodiment of the semiconductor memory device of the present invention.

14 is a timing chart for explaining the operation of a sense amplifier in the semiconductor memory device shown in FIG.

Fig. 15A is a circuit diagram showing an example of a sense amplifier drive signal generation circuit.

FIG. 15B is a timing chart for explaining the operation of the drive signal generation circuit shown in FIG. 15A. FIG.

Fig. 16A is a circuit diagram showing another example of the drive signal generation circuit of the sense amplifier.

16B is a timing chart for explaining the operation of the drive signal generation circuit shown in FIG. 16A.

FIG. 17 is a timing chart illustrating the operation of a pseudo-static type semiconductor memory device. FIG.

18 is a cross-sectional view showing an aluminum wiring according to the prior art between a memory cell element and a peripheral circuit element.

Fig. 19 is a sectional view showing an aluminum wiring according to the present invention between a memory cell element and a peripheral circuit element.

20A to 20G are cross-sectional views illustrating a method of forming aluminum wirings between the memory cell elements and peripheral circuit elements shown in FIG. 19;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a large capacity dynamic random access memory device having reduced footprint by installing sensing amplifier driving lines on sensing amplifiers and memory cells.

Recently, in the field of semiconductor memory devices, it is desired to reduce the area of each portion of the semiconductor memory device in response to the increase in the bit line capacity. In order to reduce the occupying area of each part of the semiconductor memory device, it is effective to miniaturize the structure of the semiconductor memory device and to provide efficient wiring.

In general, in a semiconductor memory device, a plurality of lines such as a bit line, a word line, a data bus, a sense amplifier driving line, a column selection line, a power line, and the like are required.

The bit lines are composed of polycrystalline silicon and a diffusion layer formed on a substrate, and the word lines are composed of polycrystalline silicon having a gate of a memory cell transistor and a metal (aluminum) wiring that assists the polycrystalline silicon to lower its resistance.

For example, the wiring layers consist of seven layers, that is, four polycrystalline silicon layers, two aluminum layers, and one diffusion layer. Sense amplifier drive lines and data buses installed in the longitudinal direction (word line direction) and column select lines in the lateral direction (bit line direction) are configured in the corresponding aluminum wiring on the memory part. However, the power lines for applying the low voltage and the high voltage to the respective sense amplifier driving lines along the longitudinal direction are not formed on the memory portion but formed transversely around the memory portion, and are connected to the data bus and the data latch circuit. Bus lines are formed transversely around the memory cell portion.

That is, a region for the power lines and the data bus lines in the transverse direction should be provided around the memory cell portion.

In addition, the plurality of sense amplifiers linearly arranged in the longitudinal direction are connected to the same sense amplifier drive lines in the longitudinal direction, thereby increasing the width of each sense amplifier drive line.

Therefore, the occupied area of the semiconductor memory device becomes large.

In addition, in the conventional semiconductor memory device, when the sensing amplifier driving lines are installed along the wand line direction (the sensing amplifier line direction), all the sensing amplifiers in the sensing amplifier line are driven by the same driving lines.

It should be noted that since the current flowing to all the sense amplifiers in the sense amplifier line flows through the drive line near the power line to the power line, the width of the drive line near the power line should be widened.

In addition, in recent years, the capacity of a DRAM device has been enlarged, and a memory cell of a DRAM is constituted by a solid structure composed of a ternary stacked capacitor cell.

This multilayer capacitor cell is useful for reducing the footprint without reducing the capacity of the memory cells.

Periphery of the memory cell portion is provided with a plurality of peripheral circuits such as a sense amplifier, a bit line driver, a row decoder, a column decoder, and the like.

These peripheral circuits are composed of normal semiconductor elements whose heights correspond to a single layer, and memory cells are composed of ternary multilayer capacitor cells whose heights correspond to a plurality of layers. Note that excessive level deviations are caused.

This level deviation does not fall within the focus area of the exposure system. Therefore, since the high precision aluminum wiring cannot be provided on the memory cell portion and the peripheral circuit portion, the footprint of the DRAM device cannot be reduced.

One object of the present invention is to provide a large capacity semiconductor memory device having a small occupied area. In addition, another object of the present invention is to provide a large-capacity semiconductor memory device having a fast operation speed.

Further, another object of the present invention is to provide a semiconductor memory device having a small peak current value due to the operation of a plurality of sense amplifiers.

According to the present invention, a plurality of word lines; This word line; A plurality of bit lines intersecting the word lines; A plurality of memory cells connected respectively between one word line and one bit line; A plurality of sense amplifiers arranged along the word line direction; First power line; A plurality of first sensing layer amplifier driving lines installed in the first wiring layer and connected to the sensing amplifier; And a plurality of second sense amplifier drive lines provided in the second wiring layer and connected between the corresponding first sense amplifier drive lines and one of the first and second power supply lines, respectively.

The first sense amplifier drive line may be installed along the word line direction, and the second sense amplifier drive line may be installed along the bit line direction.

The first sense amplifier drive line may be connected to the first and second power lines through a plurality of second sense amplifier drive lines in a plurality of parts.

The sense amplifiers and the memory cells may be divided into a plurality of blocks.

Each of the second sense amplifier drive lines may be connected to one of the first and second power lines through a gate transistor to select one of the divided blocks. The sense amplifiers may be arranged as a linear sense amplifier line along the word line direction, and each of the memory cell blocks may be divided into two groups so that the two groups are installed at both sides of the sense amplifier line.

Each block may be divided into a plurality of units.

Each of the first sense amplifier drive lines may be divided into a plurality of first unit sense amplifier drive lines corresponding to the units, and each of the second sense amplifier drive lines is connected to a corresponding first unit sense amplifier drive line. Divided into a plurality of second unit sense amplifier drive lines.

Each of the second unit sense amplifier drive lines may be connected to the first and second power lines through a gate transistor.

Since the gate transistors connected to the corresponding second unit sense amplifier drive lines in the same division block can be controlled by the same control signal, at the same timing, one of the division blocks can be selected and the units in the selected block can be selected. have.

The gate transistors connected to the corresponding second unit sense amplifier drive lines in the same division block can be controlled by one read signal and other regeneration signals, so that one unit including memory cells to be read in the selected block can be read at high speed. And the remaining units in the selected block are reproduced only at a different timing than the read operation. Since the voltage value of the read signal can be higher than that of the read signal, the read operation unit can be driven quickly and the read operation unit can be driven slowly.

The semiconductor memory device may further include a data bus line and a data latch circuit, and the data bus line may be connected between the sense amplifier and the data latch circuit.

The data bus lines are connected to the sense amplifiers in the word line direction and are connected in the bit line direction between the first data bus lines provided in the first wiring layer and between the first bus lines and the data latch circuit. And a second data bus line provided in the second wiring layer.

The second data buslines may be connected to the plurality of first data buslines and the data latch circuit through the gate transistors, and the gate transistors may be controlled by the selector, thereby selecting one of the first data buslines and selecting data. It can be connected to a latch circuit.

The first data buslines may be divided into a plurality of busline groups, and a second data busline and a data latch circuit may be installed based on the divided busline groups, and the second data buslines may be divided through a switching circuit. Since a corresponding bus line group and data latch circuit can be connected, each one of the bus line groups can be selected and connected to each data latch circuit.

The semiconductor memory device may further include signal lines provided in the first wiring layer and the second wiring layer.

The second sense amplifier drive lines may be provided between the memory cell portion and the peripheral circuit portion, and the second sense amplifier drive circuits may be connected to one of the first and second power lines through a connection conductor.

Each of the memory cells may include a multilayer capacitor and a memory cell transistor. The first wiring layer and the second wiring layer provided on the memory cells and the sense amplifiers may be used to install data bus lines, sense amplifier drive lines, other signal lines, power lines, and the like.

Further, according to the present invention, a plurality of word lines; A plurality of bit lines intersecting the word lines; A plurality of message cells each connected between one word line and one bit line; A plurality of sense amplifiers each connected to a pair of bit lines; First power line; Second power line; And a pair of sense amplifier drive layers provided in the wiring layers on the memory cells and the sense amplifiers and connected between the first and second power lines and the respective sense amplifiers.

The invention is explained in more detail by the following preferred embodiments with reference to the accompanying drawings.

First, a semiconductor memory device according to the related art will be described with reference to FIGS. 1 and 2.

In the semiconductor memory device, a plurality of word lines, bit lines, data bus lines, sense amplifier drive lines, column select lines, and power lines are provided and used. In response to the increase in capacity, the number of these lines is also increasing, and these lines cannot be installed in a single wiring layer. Therefore, recently, a multilayer wiring apparatus in which conductive lines are provided with a plurality of wiring layers has been used.

1 is a circuit diagram illustrating an example of a conventional semiconductor memory device.

Note that the circuit diagram shown in FIG. 1 corresponds to the wiring design on the semiconductor memory device (chip).

은 비트라인을 나타내며, 이 워드라인(WL)과 비트라인(BL) 및

은 반도체 메모리 장치 내에 복수로 설치돼 있다.In Fig. 1, the reference sign WL indicated in the longitudinal direction represents the word line, the cross direction BL and

Denotes a bit line, the word line WL and the bit line BL and

Is provided in plurality in the semiconductor memory device.

의 교차 구간에 메모리 셀(MC)이 설치돼 있다.Each word line WL and each bit line BL

The memory cell MC is installed at the cross section of.

In FIG. 1, only the units M ₁ and M _{11 are} shown in detail, but the other units M ₀ , M ₁ , M ₂ ,... M ₁₀ , M ₁₁ , M ₁₂ ,... Note that it has a configuration.

이 컬럼 게이트 트랜지스터(G₂)과 (G₃)를 통해서 데이타버스(DB₂)내의 대응 버스라인들에 접속돼 있다.As shown in FIG. 1, the sense amplifiers SA are arranged in the longitudinal direction or along the direction of the word line WL to form a sense amplification line, parallel to the sense amplification line or the word line WL. Along the direction are the data buses (DB ₂ ) and (DB ₃ ). In the unit M ₀ , the bit line BL and

The column gate transistors G ₂ and G ₃ are connected to the corresponding bus lines in the data bus DB ₂ .

이 컬럼 게이트 트랜지스터들을 통해서 데이타버스(DB₃)내의 대응 버스라인에 접속돼 있다. 제 1 도에 도시된 반도체 메모리 장치는 4비트 동시 독출형 DRAM장치이고, 유니트(M₀), (M₁), (M₂), (M₃) 내의 비트라인(BL) 및

은 컬럼 게이트 트랜지스터들을 통해서 데이타버스(DB₂)의 8개의 비트라인들에 접속돼 있음을 주의해야 한다. 데이타 버스(DB₂)로 독출되는 데이타는 데이타 래이치회로(DL)에 의해 래치되며, 비트라인방향(횡방향)으로 설치된 게이트 트랜지스터(G₁)과 데이타 버스(DB₁)을 통해서 외부로 독출된다.Similarly, in the unit M ₁₀ , the bit line BL and

These column gate transistors are connected to the corresponding bus lines in the data bus DB ₃ . The semiconductor memory device shown in FIG. 1 is a 4-bit simultaneous read-only DRAM device, and the bit lines BL in units M ₀ , M ₁ , M ₂ , M ₃ , and

Note that is connected to the eight bit lines of the data bus DB ₂ through column gate transistors. Data read to the data bus DB ₂ is latched by the data latch circuit DL and read out to the outside through the gate transistor G ₁ and the data bus DB ₁ provided in the bit line direction (lateral direction). do.

사이의 단락용 전원라인임을 주해야 한다. 나머지 블록 및 유니트의 구성은 블록(M₀), (M₁)과 유니트(M₀), (M₁₀)과 같다. X-디코우더(10)은 워드라인(WL)을 선택하며, Y-디코우더(W)는 비트라인을 선택한다. 이 장치에서, Y 디코우더(20)는 4쌍의 비트라인을 선택하며, 참조부호(DR)은 게이트 구동회로를 나타낸다.In FIG. 1, lines l ₁ and l ₂ are sense amplifier drive lines, and sense amplifier drive line l ₁ is a high voltage power supply line Vcc through a gate transistor G ₁₀ of a p-type MOS transistor. gotta connected to, and drive line (l ₂₎ through a gate transistor (G ₁₁₎ of the n-type MOS transistor and gotta connected to the low voltage power supply line (Vss), the operation of the sense amplifier (SA) is a gate transistor (G ₁₀₎ And (G ₁₁ ). Gate transistors (G ₄ ), (G ₅ ) and (G ₆ ), (G ₇ ) are used as cut gates, and transistors (Q ₁ ), (Q ₂ ) and (Q ₃ ), (Q ₄ ) Is used as a reset (short) transistor, and lines (l ₅ ) and (l ₇ ) are ON / OFF control signal lines of transistors (Q ₁ ), (Q ₂ ) and (Q ₃ ), (Q ₄ ) , Lines (l ₆ ) and (l ₈ ) are the bit lines (BL) and

It should be noted that the power line is for short circuit between. The configuration of the remaining blocks and units is the same as blocks (M ₀ ), (M ₁ ) and units (M ₀ ), (M ₁₀ ). The X-decoder 10 selects a word line WL, and the Y-decoder W selects a bit line. In this apparatus, the Y decoder 20 selects four pairs of bit lines, and the reference numeral DR denotes a gate driving circuit.

Memory cells are provided on both left and right sides of the sense amplification line, and when the left memory cell is selected, the right memory cell is blocked by the cut gate transistors G ₅ and G ₇ . In contrast, when the right memory cell is selected, the left memory cell is blocked by the cut gate transistors G ₄ and G ₅ .

In general, a bit line consists of polycrystalline silicon and a diffusion layer formed on a substrate. The word line is composed of polycrystalline silicon having a gate of a memory cell transistor, and metal (aluminum) wiring that assists the polycrystalline silicon to lower its resistance. When the memory cells are stacked, the memory cells are composed of two layers of polycrystalline silicon. In this apparatus, the wiring layer is composed of seven layers, that is, four polycrystalline silicon layers, two aluminum layers, and one diffusion layer. The data bus lines DB ₂ and DB ₃ , column select lines l ₃ and l ₄ installed in the longitudinal direction (along the wordline direction) are the first and second aluminum layers, respectively. It is composed of layers. The column select lines l ₃ and l ₄ are commonly used in both blocks M ₀ and M ₁₀ to reduce the occupied area of the semiconductor memory device.

However, in the semiconductor memory device shown in FIG. 1, each data bus line DB ₂ and DB ₃ are composed of eight bus lines (four pairs of bus lines), and the pitch of the bus lines is 3 占 퐉. In this case, the required width of each data bus line DB ₂ and DB ₃ is 24 μm (4 pairs × 2 × 3 μm = 24 μm). When the semiconductor memory device is a large capacity (e.g., 16M-bit) DRAM, as shown in FIG. 6, 16 cell blocks each having 1M bit capacity are provided in parallel.

It should be noted that each cell block is composed of a 2K (2048) sense amplifier (sense amplifier line) and 512K cell blocks on both sides of the sense amplifier line. Therefore, in the 16M bit-capacity DRAM, the occupied area of the total data bus line is 384 m (16 groups x 24 m = 384 m), thereby increasing the occupied area. Note that the required width of the data bus DB ₁ disposed near the memory cell portion corresponds to the width of each data bus DB ₂ and DB ₃ , so that the area for the data bus DB ₁ becomes large. 2 is an opening diagram for explaining a problem of the conventional semiconductor memory device. It should be noted that the opening degree shown in FIG. 2 corresponds to the wiring design on the semiconductor memory device (chip). As shown in FIGS. 1 and 2, in the sense amplification line, each of the sense amplifier drive lines Ln (l ₂ ) and Lp (l ₁ ) and the gate transistors provided along the word line direction (longitudinal direction) are respectively Power supply (Vss) and (Vcc) are supplied to the sense amplifier (SA). Each sense amplifier drive line drives a 2K (2048) sense amplifier and the current flowing in the drive lines Ln (l ₂ ) and Lp (l ₁ ) increases, thus driving lines Ln (l ₂ ) and Lp (l _1). It should be noted that the width of) should be determined to be about 40 μm. That is, when the number of sense amplifiers is m and the current flowing through each of the sense amplifiers is In, the total current flowing through the sense amplifier drive line Ln, in particular, flows through the drive line Ln near the gate transistor Q ₆₁ . The total current Itotal becomes a value of (In × m).

Recently, the area occupied by the sense amplifier line is not determined by the transistor size in the sense amplifier, but rather by the width of the sense amplifier drive lines Ln (l ₂ ) and Lp (l ₁ ) installed on the sense amplifier line. Is determined by For example, in the case of a 16M-bit DRAM device, the occupied area of the total sense amplifier drive line is about 1280 mu m (= 16 groups x 2 x 40 mu m), thereby increasing the occupied area of the DRAM device. Further, as shown in FIGS. 1 and 2, power lines connected to the sense amplifier drive lines Ln (l ₂ ) and Lp (l ₁ ) are provided in the word line direction near the memory portion. That is, in order to apply low and high voltage to the sense amplifier through the sense amplifier drive lines Ln (l ₂ ) and Lp (l ₁ ), the high voltage power line (Vcc) and the upper side (lower side) and the lower side (upper side) of the memory part are connected. Low voltage power lines (Vss) must be installed. In addition, since the widths of the power supply lines Vcc and Vss are large, the area occupied by the DRAM device becomes large.

One object of the present invention is to provide a large capacity small size semiconductor memory device.

A preferred embodiment of the semiconductor memory device according to the present invention will be described below with reference to the drawings.

3 is a principle diagram showing a first embodiment of the semiconductor memory device of the present invention. The opening degree and circuit diagram shown in FIGS. 3-5, 7-10, 12, and 13 correspond to the wiring design on a semiconductor memory device (chip).

, 복수의 감지증폭기(SA) 및, 데이타 버스(DB₂)와 (DB₃)로 구성돼 있다. 데이타 버스(DB₂)와 (DB₃)는 워드라인 방향으로 설치돼 있으며, 감지증폭기(SA)에 의해 증폭된 비트라인(BL)과

의 전압을 외부로 출력한다.As shown in FIG. 3, the semiconductor memory device of the first embodiment includes a plurality of word lines WL, a plurality of bit lines BL,

It consists of a plurality of sense amplifiers (SA) and a data bus (DB ₂ ) and (DB ₃ ). The data buses (DB ₂ ) and (DB ₃ ) are installed in the word line direction, and the bit lines BL amplified by the sense amplifier SA are

Output the voltage of to outside.

The data buses DB ₂ and DB ₃ are connected to the latch circuit DL via data bus lines l ₁₂ and l ₁₃ provided along the bit line direction, and furthermore, the switching circuit SW ( Gate transistors 31 and 32). The data bus lines l ₁₂ and l ₁₃ are provided on the upper side of the memory amplifier MC and the sense amplifiers SA intersecting the data buses DB ₁ and DB ₃ in one wiring layer. .

As a result, since the data bus line DB ₁ shown in FIG. ₁ can not be provided, the footprint of the semiconductor memory device can be reduced. In addition, by controlling the switching circuit SW, one data latch circuit DL can be used to receive data through two data buses DB ₂ and DB ₃ .

4 is a circuit diagram showing the first embodiment of the semiconductor memory device of the present invention. As shown in FIG. 4, the configuration of the semiconductor device of the first embodiment is similar to that of the semiconductor memory device shown in FIG. The same reference numerals as in FIGS. 1 and 2 denote the same parts in the conducting surface.

은 비트라인, (MC)는 메모리셀, (SA)는 감지증폭기를 나타낸다. 제 4 도에서, 1쌍의 비트라인(BL)과

, 이 비트라인(BL)과

에 접속된 메모리셀(MC) 및, 감지증폭기(SA)는 각각의 유니트 (블록)(M₀), (M₁), (M₂) … 및 (M₁₀), (M₁₁), (M₁₂) … , 에 포함돼 있고, 종방향(워드라인 방향)으로 배열된 복수의 유니트(M₀), (M₁), (M₂) … 및 (M₁₀), (M₁₁), (M₁₂) … 에 의해 블록(M₀) 및 (M₁)이 구성돼 있음을 주의해야 한다.That is, in FIG. 4, reference numeral WL denotes a word line, BL and

Is a bit line, MC is a memory cell, and SA is a sense amplifier. In FIG. 4, a pair of bit lines BL and

, This bit line (BL)

The memory cells MC connected to the sensing amplifier SA and the sensing amplifier SA are each unit (block) M ₀ , M ₁ , M ₂ . And (M ₁₀ ), (M ₁₁ ), (M ₁₂ ). A plurality of units M ₀ , M ₁ , and M ₂ arranged in the longitudinal direction (word line direction). And (M ₁₀ ), (M ₁₁ ), (M ₁₂ ). Note that blocks M ₀ and M ₁ are constructed by.

은 컬럼게이트 트랜지스터(G₂)와 (G₃)를 통해서 데이타 버스라인(DB₂)내의 대응 버스라인에 접속돼 있다. 이와 유사하게, 유니트(M₁₀)에서, 비트라인(BL)과

은 컬럼 게이트 트랜지스터들을 통해 데이타 버스(DB₃)내의 버스라인들에 접속돼 있다. 이 반도체 메모리 장치는, 4비트 데이타가 동시 출력되는 DRAM 장치로서, 유니트(M₀), (M₁), (M₂), (M₃)내의 비트라인(BL)과

이 컬럼 게이트 트랜지스터들을 통해서 데이타 버스라인(DB₂)의 8 버스라인들에 접속돼 있음을 주의해야 한다. 데이타 버스(DB₂)로 독출된 데이타는 데어터 버스라인(l₁₂)와 게이트 트랜지스터(31)을 통해서 데이타 래치회로(DL)에 의해 래치되며, 이와 유사하게, 데이타 버스(DB₃)로 독출된 데이타는 데이타 버스라인(l₁₃)과 게이트 트랜지스터(32)를 통해 데이타 래치회로(DL)에 의해 래치되어, 데이타 래치회로(DL)를 통해서 외부로 독출된다.In FIG. 4, the sense amplifiers SA are arranged in the word line direction to form the sense amplifier lines, and the data buses DB ₂ and DB ₃ are installed in parallel to the sense amplifier lines. In unit (M ₀ ), with bit line (BL)

Is connected to the corresponding bus line in data bus line DB ₂ through column gate transistors G ₂ and G ₃ . Similarly, in unit M ₁₀ , bit line BL and

Is connected to the bus lines in the data bus DB ₃ via column gate transistors. The semiconductor memory device is a DRAM device in which 4-bit data is simultaneously output, and the bit lines BL in the units M ₀ , M ₁ , M ₂ , and M ₃ are used.

Note that these column gate transistors are connected to the eight bus lines of the data bus line DB ₂ . Data read to the data bus DB ₂ is latched by the data latch circuit DL through the data bus line l ₁₂ and the gate transistor 31, and similarly, read to the data bus DB ₃ . Data is latched by the data latch circuit DL through the data bus line ₁₁ and the gate transistor 32, and read out to the outside through the data latch circuit DL.

The memory cells are provided on the left and right sides of the sensing amplifier line. When the left memory cells are selected, the right memory cells are blocked by the gate transistors G ₆ and G ₇ . On the contrary, when the memory cells on the right side are selected, the memory cells on the left side are blocked by the cut gate transistors G ₄ and G ₃ .

In FIG. 4, data bus lines l ₁₂ and l _{13 are} provided in the wiring layer in the transverse direction or in the bit line direction. That is, eight bus lines corresponding to eight bus lines of the data bus (DB ₂₎ (l ₁₂₎ are, between the bus lines and a data latch circuit (DL) of the data bus (DB ₂₎ provided along the left sense amplifier arrangement direction You are connected to. Similarly, the eight bus lines corresponding to eight bus lines of the data bus (DB ₂₎ (l ₁₃₎ to a bus line and a data latch circuit (DL) of the data bus (DB ₃₎ is installed along the right sense amplifier arrangement direction It is connected between. The bus line l ₁₂ and bus line l ₁₃ are commonly connected to the same data latch circuit DL through the selection gate transistors 31 and 32 controlled by the selector circuit 35. The select gate transistors 31 and 32 are not switched ON at the same time. Therefore, the same data latch circuit DL can be used for the bus lines l ₁₂ and l ₁₃ . Data read into the data latch circuit DL is output to the outside through a specific path (not shown).

The laterally arranged wiring l ₁₅ is used for another signal line, and the laterally arranged wiring l ₁₁ is Y corresponding to the signal lines l ₃ and l ₄ shown in FIG. 1. It is used for the column select line connected to the decoder 20.

5 is a circuit diagram showing a modification of the first embodiment of the semiconductor memory device according to the present invention. In FIG. 5, the sense amplifier drive lines are provided in the transverse wiring layers to form the wide wiring layers l ₁₆ and l ₁₇ . The wiring layer l ₁₆ is connected to the low voltage power supply line Vss through the gate transistor G ₁₁ , and is connected to the detection amplifier driving line l ₂ of the detection amplifier SA through the plurality of through holes H. Note that there is. Similarly, the wiring layer l ₁₇ is connected to the high voltage power supply line Vcc through the gate transistor G ₁₀ , and the sense amplifier structure line l of the detection amplifier SA through the plurality of through holes H. ₁ ) In a variation of this first embodiment, the wiring layers l ₁₇ and l ₁₇ are formed wide, and the drive lines l ₂ of the sense amplifiers on the left and right sides by the same wiring layers l ₁₆ and l ₁₇ . ) And (l ₁ ). However, the wiring layers l ₁₆ and l ₁₇ may be constituted by a plurality of wirings, and may be connected to the corresponding driving lines of the sensing amplifier driving lines l ₂ and (l ₁ ), respectively.

As described above, according to the modification of the first embodiment of the present invention, the power supply lines Vcc and Vss (wiring layers l ₁₆ and l ₁₇ ) are formed in the memory cell area and the sense amplifier area (memory cell part). Since it is installed above, the wide power supply lines Vcc and Vss can be simply not installed in adjacent areas of the memory cell portion, thereby reducing the footprint of the semiconductor memory device.

6 is an opening diagram illustrating the design of memory cell blocks and sense amplifier lines of a DRAM device. In FIG. 3, the sense amplification lines are shown as two lines, but in a large memory device such as a 16M bit DRAM device, the sense amplification lines may be multiple. As shown in Fig. 6, in a 16M-bit DRAM device, 16 cell blocks each having a capacity of 1M-bit are arranged in parallel. Note that each cell block is composed of 2K (2048) sense amplifiers (sense amplifier lines), and two 512K cell blocks are installed on both sides of the sense amplifier line. In this case, the data latch circuit DL can be commonly used for the sense amplification line, and the sense amplification line can be used by using the selector 35 and the selection gate transistors 31 and 32 shown in FIG. It doesn't work at the same time. It should be noted that the sense amplifier drive lines ι ₁₂ , ι ₁₃ and other lines are installed transversely across the sense amplifiers and reach a certain portion through the cell blocks.

7 is a principle diagram showing a second embodiment of the semiconductor memory device of the present invention.

, 복수의 감지증폭기(SA) 및 데이타 버스(DB₂₁), (DB₂₂) 및 (DB₃₁), (DB₃₂)로 구성돼 있다. 데이타 버스들(DB₂₁), (DB₂₂) 및 (DB₃₁), (DB₃₂)는 워드라인방향(종방향)을 따라 설치돼 있으며, 감지증폭기(SA)에 의해 증폭된 비트라인(BL) 및

의 전위를 외부로 출력한다. 데이타 버스들은, 워드라인방향을 따라 복수의 그룹(DB₂₁), (DB₂₂) 및 (DB₃₁), (DB₃₂)로 분할돼 있음을 주의해야 한다. 즉, 제 3 도에 도시된 데이타 버스(DB₂)는 데이타 버스(DB₂₁), (DB₂₂)로 분할돼 있고, 제 3 도에 도시된 데이타 버스 (DB₃)는 데이타버스(DB₃₁), (DB₃₂)로 분할돼 있음을 주의해야 한다. 데이타 버스(DB₂₁)과 (DB₃₁)은, 비트라인 방향을 따라 설치된 제 1 데이타 버스라인(ι₁₂)와 (ι₁₃) ALC 절환회로(SW)를 통해서, 제 1 데이타 래치회로(DL)에 접속돼 있고, 이와 유사하게, 데이타 버스(DB₂₂), (DB₃₂)는, 비트라인 방향을 따라 배열된 제 2 데이타 버스라인(ι₁₂)와 (ι₁₃) 및 절환회로(SW)를 통해 제 2 데이타 래치회로(DL)에 접속돼 있다.As shown in FIG. 7, the semiconductor memory device of the first embodiment includes a plurality of word lines WL and a plurality of bit lines BL.

It consists of a plurality of sense amplifiers (SA) and data buses (DB ₂₁ ), (DB ₂₂ ), (DB ₃₁ ) and (DB ₃₂ ). The data buses DB ₂₁ , DB ₂₂ , DB ₃₁ , and DB ₃₂ are installed along the word line direction (longitudinal direction) and are amplified by the sense amplifier SA. And

Output the potential of to outside. Note that the data buses are divided into a plurality of groups DB ₂₁ , DB ₂₂ , DB ₃₁ , and DB ₃₂ along the word line direction. That is, the data bus DB ₂ shown in FIG. 3 is divided into data buses DB ₂₁ and DB ₂₂ , and the data bus DB ₃ shown in FIG. ₃ is a data bus DB ₃₁ . Note that it is partitioned into (DB ₃₂ ). The data buses DB ₂₁ and DB ₃₁ are connected to the first data latch circuit DL through the first data bus line ι ₁₂ and ι ₁₃ ALC switching circuit SW provided along the bit line direction. Similarly, the data buses DB ₂₂ and DB ₃₂ connect the second data bus lines ι ₁₂ , ι ₁₃ and the switching circuit SW arranged along the bit line direction. It is connected to the second data latch circuit DL.

The first and second data buslines ι ₁₂ and ι ₁₃ intersect the data buses DB ₂₁ , DB ₂₂ , DB ₃₁ , and DB ₃₂ , and the memory cells MC and It is located above the detection amplifier (SA).

In addition, as shown in FIG. 7, the sense amplifier drive lines ι ₁ and ι ₂ provided with the word line direction (longitudinal direction) are connected by a plurality of wirings provided above the memory cell arrayer and the sense amplifier. Part is connected to the power lines (Vcc) and (Vss).

8 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention. The semiconductor memory device of FIG. 8 is a 16 M-bit DRAM which is the same large memory device as shown in FIG. In Figure 8, the sense amplifier lines (consisting of 2K (2048) sense amplifiers arranged linearly in the longitudinal direction) are divided into two sense amplifier lines each having 1K (1024) sense amplifiers. This semiconductor memory device is also a 4-bit simultaneous readout DRAM and requires eight data buslines, but there are only two bus lines (two pairs) for each segmented sense amplifier line.

In FIG. 8, the lines ι _12a , ι _13a , and ι _12b , ι _13b are connected to the data latch circuit DL ₁ through the switching transistor SW controlled by the selector circuit 30. , (DL ₂ ), (DL ₃ ), and (DL ₄ ), and the data latched in each data latch circuit (DL ₁ ), (DL ₂ ), (DL ₃ ), and (DL ₄ ) has a specific path. It is output to outside through (not shown). When the left sense amplifier line is in operation, the right sense amplifier line does not operate. On the contrary, when the right sense amplification line operates, the left sense amplification line does not operate. Therefore, the same data latch circuits DL ₁ , DL ₂ , DL ₃ and DL ₄ can be used for the left and right sense amplification lines.

The sensing amplifier driving lines (ι ₁ ) and (ι ₂ ) of the left and right sensing amplifier lines are respectively installed in the transverse direction of the sensing amplifier driving lines (ι ₃₁ ), (ι ₃₂ ) and (ι ₄₁ ) and (ι _42). It is connected to the low voltage power supply line Vss and the high voltage power supply line Vcc through the gate transistors G ₁₁ and G ₁₀ . That is, the sense amplifier drive line ι ₁ is connected to the high voltage power line Vcc through the sense amplifier drive lines ι ₃₂ and ₄₂ and the gate transistor G ₁₀ , and the sense amplifier drive line ι _2. ) Is connected to the low voltage power supply line Vss through the sense amplifier drive lines? ₃₁ and? ₄₁ , and the gate transistor G ₁₁ . Each sense amplifier drive line ι ₁ is connected to the power supply line Vcc by a plurality of (2) drive lines ι ₃₂ and (ι ₄₂ ), and each sense amplifier drive line ι _{2 is} provided in plurality. It is connected to the power line (Vss) by the driving line (ι ₃₁ ) and (ι ₄₁ ) of ( ₂ ), and the current flowing through each of the sensing amplifier driving lines (ι ₁ ) and (ι ₂ ) It is divided into (ι ₃₂ ), (ι ₄₂ ) and (ι ₃₁ ), (ι ₄₁ ). Therefore, the sense amplifier driving line can be reduced to the width of each of (ι ₁₎ and (ι _2), it is possible to reduce the area occupied by the sense amplifier driving line (ι ₁₎ and (ι _2).

As described above, the sense amplifier drive lines ι ₃₁ , ι ₃₂ , ι ₄₁ , and ι ₄₂ installed in the transverse direction are provided in plural, and the sense amplifier drive lines ι installed in the longitudinal direction (ι ₃₁ ). ₁ ) and (ι ₂ ) are supplied with power Vss and Vcc through the plurality of driving lines, and thus, the width of each driving line ι ₁ and ι ₂ may be reduced.

By dividing the sense amplifier lines into two groups of sense amplifier lines along the longitudinal direction in a 16M-bit DRAM device, the width of the data bus can be reduced to 384/2 = 192 μm, and the width of the sense amplifier drive line is 1280 /. It can be reduced to 2 = 640 mu m.

FIG. 9 is an opening circuit diagram showing a part of the semiconductor memory device shown in FIG. 8, in which the design of each layer wiring arranged in the transverse direction is shown in one group composed of 16 sense amplifiers. In FIG. 9, reference numerals SA _{1 to} SA ₁₆ represent 16 sense amplifiers, and (BL ₁ ) to (BL ₁₆ ) represent 16 pairs of word lines. Further, reference numeral C1: C2 denotes column selection lines, (G ₂₁ ), (G ₂₂ ). And the like represent column select gate transistors, which are denoted by reference numerals ι ₃ , G ₂ , and G ₃ in FIG. 8. Also, reference numerals DBa and DBb denote four data bus pairs DB ₂₁ ,. And the like.

The two pairs of bit lines include column select lines C1, C2,... It is connected to the corresponding data bus pair DBa and DBb by one of them, and 4-bit data is simultaneously output by a 16 sense amplifier (not shown). In the present embodiment, the bit line pairs BL ₁ and BL ₃ are controlled by the column select lines C1, are connected to the data bus pairs DBa and DBb, and the bit line pairs BL _2. ) And (BL ₄ ) are controlled by column select lines C2, connected to data bus pairs DBb and DBa, and the other bit line pairs are also controlled by column select lines as described above. It is connected to the corresponding data bus pair.

If the lateral direction of the first wiring (column select line), which is installed to the first sense amplifier vapor, may be provided 16 transverse wires 16 on the sense amplifier (SA ₁ ~SA _16). Since one column select line C1 to C8 processes the two bit line pairs BL _{1 to} BL ₁₆ , and only eight column select lines are sufficient, 8 installed on the sense amplifiers SA _{5 to} SA _{12 of} FIG. Space corresponding to the wiring lines can be maintained. That is, in this embodiment, the column select lines are provided in the upper part by four lines C1 to C4, and are arranged in the lower part by four lines C5 to C8. Therefore, there is a space margin of 8 lines in the center part, and power lines Vss, Vcc and other signal lines (e.g. line ι ₃₁ in FIG. 8), or data. A bus DBc (e.g., lines ι _12a , ι _13a ); ι _12b , ι _{13b in} FIG. 8 can be installed in the eight margin lines in the central part.

As described above, according to the second embodiment of the present invention, particularly in a large-capacity semiconductor memory device, it is possible to reduce the width of the sense amplifier drive lines and the data bus lines installed along the sensing amplifier lines (longitudinally). Therefore, the occupied area can be significantly reduced.

10 is a circuit diagram showing a third embodiment of the semiconductor memory device of the present invention. In FIG. 10, all memory cells are divided into four blocks A through D in the bit line direction (lateral direction), and each block A through D has four units along the word line direction (longitudinal direction). Blocks). For example, block A is divided into units 1A, 1B, 1C, and 1D. Each block A to D includes one sensing amplifier line in which the sense amplifiers are arranged linearly in the longitudinal direction, and the two memory cell lines (blocks) in the longitudinal direction have a plurality of memory cells. 2 Memory cell blocks are installed on both sides of the sense amplifier line. In practice, however, memory cells are not divided into four blocks in each direction, but divided into 32 or 64 blocks in each direction.

As shown in Fig. 10, in each of the blocks A to D, the sense amplifier drive lines Ln and Lp provided in the longitudinal direction are each four wires (sensing amplifier drive lines) L1n to L4n. And (L1p to L4p). The wirings L1n to L4n are connected to corresponding wirings (sensing amplifier driving lines) SAN1A to SAN4A provided in the lateral direction, and the sensing amplifier driving lines L1p to L4p are provided along the transverse direction. It is connected to the corresponding wiring (SAP1A)-(SAPA). Since the wirings SAN1A to SAN4A and SAP1A to SAP1A are provided in one wiring, which is another layer having the wirings L1n to L4n and (L1p to L4p), the wirings SAN1A to SAN4A and (SAN4A), ( SAN1B) to (SAN4B), (SAN1C) to (SAN4C), (SAN1D) to (SAN4D) and wirings L1n to (L4n) and (L1p) to (L4p) in the same manner as the circuit diagram shown in FIG. Note that it can be configured. For example, the wirings SAN1D to SAN4D for connection between the sensing amplifier SA and the low voltage power supply line Vss in the block D are disposed on the blocks A, B, and C. And wirings (SAP1A) to (SAP4A) for connection between the sense amplifiers in the block (A) and the high voltage power supply line (Vcc) on the blocks (B), (C) and (D). have. The wirings L1n to L4n (Ln) and (L1p) to (L4p) (Lp) are provided on the sensing amplifier line, and the occupied area for the sensing amplifier line is the wiring L1n to L4n (Ln) and (L1p). Note that it is limited by the size of (L4p) (Lp).

In the conventional semiconductor memory device, when the sense amplifier drive lines Ln and Lp are arranged along the word line direction (the sense amplifier line direction) as shown in FIG. 2, all the sense amplifiers in the sense amplifier line are disposed. It is driven by the same drive line Ln and Lp.

Since the current flowing to all the sense amplifiers in the sense amplifier line flows through the drive lines Ln and Lp near the power lines Vss and Vcc, the drive lines near the power lines Vss and Vcc ( Note that the width of Ln) and (Lp) should be increased. However, in this embodiment, the sense amplifier drive lines Ln and Lp in FIG. 2 are divided into four wires L1n to L4n and L1p to L4p, and each of these wires corresponds to a corresponding wiring SAN1A. It is connected to the low voltage power supply line Vss and the high voltage power supply line Vcc provided in the word line direction through-(SAN4A) and (SAP1A)-(SAP4A). Therefore, the widths of the respective sense amplifier drive lines L1n to L4n and L1p to L4p can be reduced by the number of the sense amplifier drive. That is, in the prior art, the sensing amplifier driving lines Ln and Lp are driven by the same sensing amplifier driving lines Ln and Lp of all the sensing amplifiers in the sensing amplifier line, so that sufficient current is supplied to the connected sensing amplifiers. Becomes wider.

However, in this embodiment, the sense amplifiers in each sense amplifier line are divided into four blocks (units 1A to 1D), and the sense amplifier drive lines Ln and Lp are divided into four wires L1n to L4n and ( It is divided into L1p to L4p, and the low and high voltages (Vss) and these wirings L1n to L4n and L1p to L4p are connected through the corresponding wirings (SAN1A) to (SAN4A) and (SAP1A) to (SAP4A). (Vcc) is supplied. Therefore, in the present invention, the widths of the sensing amplifier driving lines L1n to L4n and L1p to L4p are small, and the area of the sensing amplifier lines on which the wirings L1n to L4n and L1p to L4p are provided is small. Lose.

Further, in the present embodiment, the power lines Vss and Vcc arranged around the memory portion along the longitudinal direction (word line direction or sense amplification line direction) and the wirings SAN1A to (or along the transverse direction) are provided. By using SAN4A) and (SAP1A) to (SAP4A), the power supply lines Vss and Vcc provided in the circumferential direction (bit line direction) around the memory portion can not be provided. The length of the memory cell portion in the lateral direction is longer than that of the memory cell portion in the longitudinal direction, and the wirings (SAN1A) to (SAN4A) and (SAP1A) to (SAP4A) are provided on the memory cell portion, thereby occupying the power line. Note that the area is smaller.

신호가 실행되고, 워드라인선택용 어드레스가 정해지면, 식별되는 워드라인이 블록(A)∼(D)에 속하게 되고, 그러면, 4감지증폭기실행(activation) 클록(SENA)∼(SEND)중 하나가 발생된다. 예를들어, 블록(A)내의 워드라인이 구동되면, 감지증폭기 실행클록(SENA)이 고레벨로 바뀌고, 감지증폭기 구동 트랜지스터(Q₁), (Q₅), (Q₉) 및 (Q₁₃)이 ON되고, 그 다음 감지증폭기 구동라인(SAN1A)∼(SAN4A)가 저전압 전원라인(Vss)에 접속되어, 블록(A)내의 감지증폭기만 실행되며, 블록(B), (C) 및 (D)내의 다른 감지증폭기들은 실행되지 않는다. 감지증폭기 실행클록(SENA)이 바뀌면, 대응하는 실행클록(SEPA)로 변경되며, 감지증폭기 구동 트랜지스터(Q₁₇), (Q₂₁), (Q₂₅) 및 (Q₂₉)도 ON되며, 다음 감지증폭기 구동라인(SAP1A)∼(SAP4A)이 고전압 전원라인(Vcc)에 접속된다.In Fig. 10, reference numerals Q _{1 to} Q ₁₆ denote sense amplifier driving transistors (gate transistors), and these transistors are usually turned off.

When the signal is executed and the word line selection address is determined, the word line to be identified belongs to blocks (A) to (D), and then one of the four sense amplifier activation clocks SENA to SEND. Is generated. For example, when the word line in block A is driven, the sense amplifier execution clock SENA changes to high level, and the sense amplifier drive transistors Q ₁ , Q ₅ , Q ₉ and Q ₁₃ . Is turned on, and then the sense amplifier drive lines SAN1A to SAN4A are connected to the low voltage power supply line Vss so that only the sense amplifiers in the block A are executed, and the blocks B, C and D are executed. The other sense amplifiers in) are not executed. When the sense amplifier execution clock (SENA) is changed, it is changed to the corresponding execution clock (SEPA), and the sense amplifier driving transistors (Q ₁₇ ), (Q ₂₁ ), (Q ₂₅ ) and (Q ₂₉ ) are also turned on and the next sense The amplifier drive lines SAP1A to SAP4A are connected to the high voltage power supply line Vcc.

In the above description, the widths of the single sense amplifier drive lines SAP1A to SAP4A can be reduced by increasing the number of divisions, and thus, the sense amplifier drive lines in the same wiring layer in which data bus lines and column select lines are installed. Can be installed.

FIG. 11 is a cross-sectional view illustrating a part of the semiconductor memory device shown in FIG. 10. Provided in _{the; (ι 2, ι 1 L1n~L4n} , L1p~L4p) a first wiring layer (W ₁₎ of claim 10 also, the plurality of the word line direction the sense amplifier driving line (Ln) and (Lp) as shown in And the second plurality of sensing amplifier drive lines SAP1A to SAP4A, ... SAP1A to SAP4A, ... ι ₃₁ , ι ₄₁ , ι ₃₂ , ι _{42 in the} bit line direction are provided in the second wiring layer W ₂ . . It should be noted that these wiring layers W ₁ and W ₂ are provided on the memory cell portion including the plurality of memory cells and the sense amplifiers.

FIG. 12 is a cross-sectional view illustrating a part of the semiconductor memory device shown in FIG. 10.

In FIG. 12, reference numerals Q _{41 to} Q ₄₄ denote transistors constituting the sense amplifier SA1, and reference numerals Q _{49 to} Q ₅₀ denote gate transistors for column selection, and the gate transistor Q Gates _{49 to} Q ₅₀ are connected to the output wiring CL1 of the column decoder provided at the end of the memory cell portion (memory cell array). The wiring CL1 is provided in the second aluminum wiring W ₂ provided along the bit line direction or in the word line direction. In Fig. 12, reference numerals Q _{45 to} Q ₄₈ denote switching transistors for the shared sense amplifiers. In the sense amplifier SA1, it should be noted that the sense amplifier drive lines L1n and L1p are installed in the longitudinal direction in the first aluminum wiring layer W ₁ . The configuration of the sensing amplifier SA2 is the same as that of the sensing amplifier SA1, and the sensing amplifier SA2 is not required in the vicinity of the sensing amplifier SA1. As shown in FIG. 12, a sensing amplifier driving line (SAN1A) and (SAP1A) for driving the sensing amplifier installed in the block A (unit 1A) are provided in one region of the sensing amplifier SA2. The driving lines SAN1A and SAP1A are provided in the second wiring layer W ₂ and connected to the sensing amplifier driving lines L1n and L1p, respectively. Reference sign SA3 denotes a sense amplifier (shared sense amplifier) in the same block A. In this block, another sense amplifier drive line SAN1B for driving a sense amplifier installed in the block B (unit 1B) is provided. The drive line SAN1B is provided in the second wiring layer W ₂ on the sense amplifier SA3 through the insulating layer.

As described above, the sense amplifier drive lines SAP1A to SAP4A, ... SAP1A to SAP4A, ... are provided in the second wiring layer W ₂ on the sense amplifier SA, and thus are arranged along the transverse direction. When the array is divided into a plurality of blocks in the bit line direction, the sense amplifier driving lines may be installed on the memory cell array.

13 is an opening circuit diagram showing a modification of the third embodiment of the semiconductor memory device according to the present invention.

In FIG. 13, the sense amplifier drive transistors are divided into four blocks in the word line direction, and each drive transistor in the division block is independently controlled by the sense amplifier execution clock. That is, for example, the sense amplifier execution clock SENA for controlling the sense amplifier driving transistors Q ₁ , Q ₅ , Q ₉ and Q ₁₃ shown in FIG. It is divided into amplifier execution clocks SEN1A to SEN4A. For example, it should be noted that the sense amplifier drive transistor Q ₁ is controlled by the sense amplifier execution clock SEN1A and the sense amplifier drive transistor Q ₅ is controlled by the sense amplifier execution clock SEN2A. Similarly, the sense amplifier execution clock SEPA for controlling the sense amplifier drive transistors Q ₁₇ , Q ₂₁ , Q ₂₅ and Q ₂₉ shown in FIG. It is divided into sense amplifier execution clocks SEP1A to SEP4A. By subdividing the sense amplifier execution clock, for example, in the semiconductor memory device shown in FIG. 10, upon access of the first block (unit) 1A in the block A, the sense amplifier execution clock SENA is executed. Changed to high level. However, in the semiconductor memory device shown in FIG. 13, the voltages of the execution clock SEN1A for the read operation and the execution clocks SEN2A to SEN4A for the read operation are different. That is, the voltage difference of the execution clock SEN1A for the read operation is higher than that of the execution clocks SEN2A to SEN4A dedicated to the reproduction operation. The unit 1A is driven strongly by the execution clock SEN1A, or the data bus to the unit 1A is driven by low impedance (the internal resistance of the sense amplifier in the unit 1A is small), and from the memory cell The circuit operation speed for reading data becomes faster.

In addition, the other units 2A to 4A that perform only the reproducing operation are driven weaker than the unit 1A, and the operation speed in the units 2A to 4A becomes slow. Therefore, the generated current at the start of operation in the units 1A to 4A can be reduced. In the present embodiment, there are only four division units (blocks), but in practice, the division units may be 32 division units. That is, when all the sense amplifiers are divided into 32 blocks, only 1/32 of all blocks are required for high speed operation (read operation), and the remaining 31/32 blocks only perform the regeneration operation of the memory cell. The average current or total current flowing through all the sense amplifiers is invariant, but the current carrying timing may be different in the sense amplifiers involved in the read operation and the rest of the sense amplifiers involved in the regeneration operation, thereby reducing internal noise and malfunction in the semiconductor memory device. Be careful.

FIG. 14 is a timing chart illustrating the operation of the sense amplifier preferred for the semiconductor memory device shown in FIG.

)클록을 저레벨로 변경하면, 로우 어드레스는 칩(반도체 메모리 장치)내로 취출되고, 이 로우 어드레스에 대응하는 워드라인이 선택되고, 감지증폭기 실행클록(SEN1A)~(SEN4A) 각각이 고레벨로 변경된다. 블록(A)내의 모든 선택된 감지증폭기가 감지증폭기 실행클록(SEN1A)∼(SEN4A)에 의해 동시에 동작한다.In Figure 14, the row address strobe (

When the clock is changed to the low level, the row address is taken out into the chip (semiconductor memory device), the word line corresponding to the row address is selected, and each of the sense amplifier execution clocks SEN1A to SEN4A is changed to the high level. . All selected sense amplifiers in the block A are operated simultaneously by the sense amplifier execution clocks SEN1A to SEN4A.

It should be noted that since all sense amplifiers in block A are driven with approximately the same current value, the drive current flowing through each sense amplifier is small and the operation speed is slow.

The reason why the current flowing through each of the sense amplifiers is almost the same is that the gate voltage of each sense amplifier driving transistor is limited to about 1/2 of the power supply voltage, and the operation of each driving transistor is applied to the electric pipe having a constant current characteristic. It is because it is disclosed in the range similar to a pentagonal tube characteristic.

)클록이 저레벨로 변경된 후 약 20ns∼30ns 후에, 컬럼 어드레스 스트로브

클록이 저레벨로 변경되어, 컬럼 어드레스가 칩내로 취출된다. 이 경우, 억세스하는 컬럼의 속성블록(attribute block)이 식별될 수 있으며, 따라서, 동작 전압치와, 구동 또는 선택을 위해서 감지증폭기 구동 트랜지스터의 게이트에 공급되는 감지증폭기 실행클록(SEN1A)이, 재생전용 및 비선택용의 감지증폭기의 구동 트랜지스터의 게이트에 공급되는 나머지 클록들(SEN2A)∼(SEN4A)의 레벨보다 더 고레벨로 정해진다.(

Column address strobe approximately 20 ns to 30 ns after clock is changed to low level

The clock is changed to the low level so that the column address is taken out into the chip. In this case, an attribute block of the accessing column can be identified, so that the operating voltage value and the sense amplifier execution clock SEN1A supplied to the gate of the sense amplifier driving transistor for driving or selection are reproduced. The level is set higher than the level of the remaining clocks SEN2A to SEN4A supplied to the gates of the drive transistors of the dedicated and unselected sense amplifiers.

This selection operation is performed by decoding part of the column address. For example, if there are 4 partitioning blocks, 2 bits of column address are decoded, and in the case of 32 partitioning block, 5 bits of column address are decoded as 32 can be represented by 2 ⁵ .

Therefore, the sense amplifiers in only one unit (block) 1A are driven in high speed operation. Note that the amplitude of the bit lines in unit 1A is greater or higher than that of the remaining units 2A-4A. Also, since the number of bits decoded in the column decoder is larger than the number of bits decoded for block selection, the operation speed of the block selection is faster than that of the column decoder.

As described above, the sense amplifier in the unit 1A drives the column switches (Q ₄₉ and Q ₅₀ in FIG. 12) corresponding to the access column, and since the sense amplifier drives the data bus line strongly, Circuits up to the data output amplifier can be driven first. On the other hand, the sense amplifiers in the non-selecting units 2A to 4A are driven slowly (weakly), so that the current flowing in the sense amplifiers at the start of operation is not large. In these unselected units 2A to 4A, the reproducing operation is executed until the RAS cycle is completed.

Specifically, the sense amplifiers in the unselected units are suitable for performing the amplification operation for a long period of 40ns to 50ns. In this embodiment, the current flowing to the sense amplifier does not flow at the start of operation but flows thereafter.

FIG. 15A is a circuit diagram showing an example of a sense amplifier drive signal generation circuit, and FIG. 15B is a timing chart for explaining the operation of the drive signal generation circuit shown in FIG. 15A.

클록은 감지증폭기 구동신호이며, 정상 상태에서는 고레벨(Vcc)이며, 이것은

클록을 사용하여 발생된다.As shown in Figs. 15A and 15B,

The clock is the sense amplifier drive signal, which is high level (Vcc) in normal state.

It is generated using a clock.

클록에 의해 ON되고, 상기 (Vcc)레벨보다 트랜지스터(Q₁₀₁, Q₁₀₂)의 임계치만큼 낮은 특정 레벨의 클록(SEN1A)이 발행되고, 따라서 감지증폭기가 약하게(느리게)구동된다. 컬럼어드레스가 해독되고, 억세스 블록(선택된 블록)이 식별되며, 이 억세스 블록내의 선택신호(BS1)가 Vcc 레벨로 변경되고, NAND 게이트(G1)의 출력이 저레벨(Vss)로 변경된다. 그러므로, 트랜지스터(Q₁₀₄)가 ON되고, 클록(SEN1A)이 Vcc 레벨로 변경되어, 유니트(1A)내의 감지증폭기가 빠르게(강력하게)구동된다. 재생동작만을 행하는 블록(2A)∼(4A)에서는, 블록선택 신호가 Vss 레벨에 유지되어, 트랜지스터(Q₁₀₄)에 대응하는 트랜지스터의 동작속도가 느리게 유지된다.Transistor Q ₁₀₀ is

A clock SEN1A of a specific level, which is turned on by the clock and is lower by the threshold of transistors Q ₁₀₁ and Q ₁₀₂ than the (Vcc) level, is issued, and therefore the sense amplifier is weakly (slowly) driven. The column address is decoded, the access block (selected block) is identified, the select signal BS1 in this access block is changed to the Vcc level, and the output of the NAND gate G1 is changed to the low level Vss. Therefore, the transistor Q ₁₀₄ is turned on, and the clock SEN1A is changed to the Vcc level, so that the sense amplifier in the unit 1A is driven quickly (strongly). In blocks 2A to 4A which perform only the regeneration operation, the block select signal is held at the Vss level, and the operation speed of the transistor corresponding to the transistor Q ₁₀₄ is kept low.

FIG. 16A is a circuit diagram of another example of the drive signal generation circuit of the sense amplifier, and FIG. 16B is a timing chart illustrating the operation of the drive signal generation circuit shown in FIG. 16A.

As described above with reference to FIGS. 15A and 15B, the operating speed of the selected sense amplifier may be different from that of the non-selective sense amplifier by changing the gate voltage of the driving transistor. 16A and 16B, however, the sense amplifier driving transistor is composed of two transistors of different sizes. In other words, the sensing amplifier can be driven by both large transistors and small transistors. Note that the large transistors are controlled by the sense amplifier drive clocks SEN1AA (and SEP1AA) and the small transistors are controlled by the sense amplifier drive clocks SEN1A (and SEP1A). In this drive signal generation circuit, the sense amplifiers in all the units 1A to 4A at the start of operation are driven by receiving the drive clock SEN1A by small transistors, and after the block selection signal output, the selected unit 1A It is to be noted that the sense amplifier corresponding to C) is driven by receiving the drive clock SEN1AA by the large transistors.

17 is a timing chart for explaining the operation of the pseudo-static static memory device.

클록에 대응하는

클록신호가 저레벨로 변경되면, 어드레스 멀티플렉스 동작이 실행되지 않고, 로우 사이드(row side)와 컬럼 사이드(column side)양자의 어드레스들이 칩내로 취출된다. 이러한 슈-도 스태틱형 DRAM 장치에서는, 동작 개시시에 억세스하는 컬럼 블록(선택된 컬럼 블록)이 정해지기 때문에, 감지증폭기들이 고속동작 유니트와, 동작 개시시에 재생동작만 행해지는 저속 동작 유니트로 분할될 수 있다. 다른 동작들은 제 14 도에서의 경우와 같다.As shown in FIG. 17, in the pseudo-dominated DRAM device,

Corresponding to the clock

When the clock signal is changed to the low level, the address multiplex operation is not executed, and the addresses of the row side and column side quantums are taken out into the chip. In such a pseudo-static DRAM device, since a column block (selected column block) to be accessed at the start of operation is determined, the sense amplifiers are divided into a high speed operation unit and a low speed operation unit in which only a regeneration operation is performed at the start of operation. Can be. The other operations are the same as in the case of FIG.

As described above, according to the third embodiment of the present invention, the width of the sense amplifier drive lines can be reduced by increasing the number of divisions thereof, and thus the width or sense amplification of the sense amplifier drive lines installed in the word line direction. The footprint of the line can be reduced. Also, since the sense amplifier driving lines can be installed in the same wiring layer in which the data bus lines and the column select lines are installed, the footprint of the semiconductor memory device can be reduced. In addition, by subdividing the sense amplifier execution clocks, the timing of the current flowing in the sense amplifiers involved in the read operation and the remaining sense amplifiers only involved in the reproduction operation can be different, thereby preventing internal noise and malfunction in the semiconductor memory device. Can be reduced.

In addition, the capacity of the DRAM device is increased, and the memory cell of the DRAM is composed of a solid structure consisting of ternary stacked capacitor cells. This stacked capacitor cell is useful for reducing the footprint of a memory cell without reducing its capacity. Around the memory cell portion, a plurality of peripheral circuits, for example, a sense amplifier bit line driver, a row decoder, a column decoder, and the like are provided. Since these peripheral circuits are composed of regular semiconductor elements whose heights correspond to a single layer, and the memory cells are composed of ternary stacked capacitor cells whose heights correspond to a plurality of layers, the memory cell portion is divided between the peripheral circuit portions. It should be noted that excessive deviation is caused at the boundary of.

18 is a cross-sectional view showing an aluminum wiring between a memory cell element and a peripheral circuit element according to the prior art.

The aluminum wiring may be used in place of the data bus line or the sense amplifier drive lines installed along the transverse direction (bit line direction) in the wiring layer W ₁ or W _{2 in} FIG.

In Fig. 18, reference numeral 1 denotes a memory cell element, 2 a peripheral circuit element, 3 a p-type silicon substrate, 4 an electric field insulating film, and 5 a stacked capacitor. Reference numeral 6 denotes a peripheral circuit wiring made of aluminum wiring, which is used as data bus lines or sense amplifier driving lines arranged in the lateral direction, and the peripheral circuit element 2 is replaced with another peripheral circuit element (not shown). It should be noted that it is used as a wiring (peripheral circuit wiring) for connection to the (not connected).

As shown in FIG. 18, in the conventional semiconductor memory device, a large level difference occurs in the boundary portion between the memory cell portion and the peripheral circuit portion. This level difference between the memory cell portion and the peripheral circuit portion cannot be accommodated in the focal region of the exposure system. Therefore, since the aluminum wiring cannot be freely installed with high accuracy on the memory cell portion and the peripheral circuit portion, the occupied area of the DRAM device cannot be reduced.

19 is a cross-sectional view showing the aluminum wiring between the memory cell element and the peripheral circuit element according to the present invention.

In Fig. 19, reference numeral 1 denotes a memory cell element, 2 denotes a peripheral circuit element, 3 denotes a p-type silicon substrate, 4 denotes an electric field insulating film, and 5 (5C) a multilayer capacitor. 6 shows aluminum wiring (data bus line, sense amplifier drive line, peripheral circuit wiring), 5T shows a memory cell transistor, and 7 shows a tungsten (W) connecting conductor. Specifically, for example, in the case where the memory cell element 1 is provided at 5000 mV and the connection conductor 7 is installed at 3000 mV on the peripheral circuit element 2, the level difference between the memory cell part and the peripheral circuit part is 2000 dB, and this level difference can be accommodated in the focus area of the exposure system. Therefore, the aluminum wiring can be freely installed with high accuracy on the memory cell portion and the peripheral circuit portion, thereby reducing the footprint of the DRAM device. That is, by providing the wiring on the memory cell portion and the peripheral circuit portion as described above with reference to Figs. 3 to 10, the area occupied by the wiring can be reduced, and thus a large scale integrated DRAM device is obtained.

20A to 20G are cross-sectional views illustrating a method for installing aluminum wiring between the memory cell element and the peripheral circuit element shown in FIG.

First, as shown in FIG. 20A, the electric field insulating film 4 is provided on the p-type silicon substrate 3, and the first polycrystal is formed on the silicon substrate 3 through the gate insulating film 11 (about 100 microns thick). A gate electrode of silicon film P ₁ (about 100 microns thick) is provided. Next, using the gate electrode and the electric field insulating film 4 as a mask, non-arsenic ions are implanted into the silicon substrate 3 to form a source region S and a drain region D. Next, a silicon dioxide (SiO ₂ ) film 12 is provided on the silicon substrate 3, and through the contact holes on the source region S, on the holes, a second polycrystalline silicon film coated with tungsten silicide. Install the bit line (P ₂ ).

Next, as shown in FIG. 20B, a Si ₃ N ₄ (silicon nitride) film 13 (about 500 microns thick) is provided on the SiO ₂ film, and a second polycrystalline silicon film P ₂ or a silicon substrate ( 3), four SiO ₂ films 14 and three polycrystalline silicon films 15 are alternately provided. Next, in order to form the contact portion of the multilayer capacitor, the drain region D is penetrated through the SiO ₂ film 14, the polycrystalline silicon film 15, and the Si ₃ N ₄ film 13 by lithography. The hole is drilled to the surface, and a polycrystalline silicon film 16 (about 1000 microns thick) is provided thereon to form a tree capacitor. It should be noted that the total thickness from the surface of the substrate 3 to the trademark surface layer of the polycrystalline silicon film 16 (except for the Si ₃ N ₄ film 13) is about 5000 kPa.

Next, as shown in FIG. 20C, the polycrystalline silicon films 16 and 15 and the SiO ₂ films 14 (except the lowest SiO ₂ film) are removed by lithography in the region except the stacked capacitor portion. A tree stacked capacitor is formed.

Next, as shown in FIG. 20D, in the region of the multilayer capacitor portion, SiO ₂ films 14 between the polycrystalline silicon films 16 and 15 are removed by etching by dipping hydrochloric acid solution. Thus, the tree-shaped polycrystalline silicon films 16 and 15 are left. The tree polycrystalline silicon films 16 and 15 are referred to as the third polycrystalline silicon film P ₃ .

It should be noted that in the manufacturing method of the multilayer capacitor, the Si ₃ N ₄ film 13 is used to stop etching on the surface of the film.

Next, as shown in FIG. 20E, by using a thermal oxidation method, a dielectric film (marked with a thick line) on the third polycrystalline silicon film P ₃ (tree type polycrystalline silicon films 16 and 15) is shown. ), And then a fourth polycrystalline silicon film P ₄ (about 1000 mm thick) is placed thereon.

In the region of the following, non-layered capacitor portion, the fourth by removing the polycrystalline silicon film (P _4), a fourth polysilicon film (P ₄₎ remaining in the layered capacitor portion becomes a cell plate (plate).

As described above, after the multilayer capacitor 5 is formed, an SiO ₂ film 17 (about 1000 mm thick) is provided on the multilayer capacitor 5.

Referring to FIG. 20F, almost all main parts of the memory cell element 1 and the peripheral circuit element 2 are provided, followed by the SiO ₂ film 17, the Si ₃ N ₄ film 13, and the SiO. ₂ Contact holes are drilled through the membrane 12 to the electrode portions. Next, if a tungsten (W) film 7 (about 3000 microns thick) is provided using chemical vapor deposition (CVD), and the tungsten film 7 is patterned as a connecting conductor using the next lithography method, the connecting electrode height Is released.

Finally, as shown in FIG. 20G, a phospho-silicate glass (PSG) film 18 is provided on the SiO ₂ film 17 and the tungsten film 7, and the next memory By providing the aluminum wiring 6 on the cell element 2, a bus line sensing amplifier drive line or peripheral circuit wiring can be provided.

That is, the aluminum wiring 6 is connected to the drain region D of the peripheral circuit element 2 through the connection conductor 7 of the tungsten film, whereby the level difference between the memory cell portion and the peripheral circuit portion is reduced. This level difference can be accommodated in the focal region of the exposure system, and therefore aluminum wiring can be freely provided with high accuracy on the memory cell portion and the peripheral circuit portion. Specifically, by providing the wiring on the memory cell portion and the peripheral circuit portion, the occupied area of the wiring can be reduced, and thus a large scale integrated DRAM can be obtained.

In the semiconductor memory device of the fourth embodiment of the present invention, the connecting conductor 7 is not limited to the tungsten film, and the connecting conductor 7 may be made of polycrystalline silicon, tungsten silicide (WSi ₂ ), or the like.

As various modifications are possible within the spirit of the invention, the invention is not limited by the above embodiments but only by the claims.

Claims (21)

A plurality of word lines WL; A plurality of bit lines BL intersecting the word lines WL

); The 1 word line WL and the 1 bit line BL,

A plurality of memory cells MC each connected between the plurality of memory cells; A plurality of sense amplifiers SA arranged along the word line direction WL; First power line Vss; Second power supply line Vcc; A plurality of first sensing amplifier driving lines connected to the sensing amplifiers SA and installed in a first wiring layer W ₁ (ι ₂ , ι ₁ ; Ln, Lp); And corresponding first sensing amplifier driving lines ι ₂ , ι ₁ ; Ln, Lp and one of the first and second power lines Vss and Vcc, respectively, and the second wiring layer W ₂ ) a semiconductor memory device comprising a plurality of second sense amplifier drive lines ( ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ ; SAN, SAP) installed in the circuit. The method of claim 1, wherein the first sense amplifier driving line (ι ₂ , ι ₁ ; Ln, Lp) is installed in the word line direction (WL), the second sense amplifier driving lines (ι ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ ; SAN, SAP) is a memory device characterized in that installed in the bit line (BL) direction. The method of claim 1, wherein the first sense amplifier driving lines (ι ₂ , ι ₁ ; Ln, Lp), the plurality of second sense amplifier driving lines (ι ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ ; SAN) And a plurality of portions connected to the first and second power lines (Vss, Vcc) through SAP. The semiconductor memory device of claim 1, wherein the sensing amplifiers SA and the memory cells MC are divided into a plurality of blocks M ₀ , M ₁ ; A, B, C, and D. 4. . 5. The method of claim 4, wherein the second sense amplifier driving lines ι ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ pass through the first and second power lines Vss and Vcc through gate transistors G ₁₁ and G ₁₀ . And one of the partition blocks (M ₀ , M ₁ ) is selected. The method of claim 4, wherein the sense amplifiers SA are arranged as linear sense amplifier lines in the direction of the word line WL, and each of the blocks M ₀ , M ₁ ; A, B, C, D The semiconductor memory device according to claim 1, wherein the memory cells are divided into two groups on both sides of the sensing amplification line. The method of claim 4, wherein each of the blocks A, B, C, and D has a plurality of units 1A, 2A, 3A, 4A, 1B, 1B, 3B, 4B, 1C, 2C, 3C, 4C, 1D, 2D, 3D, and 4D). The method of claim 7, wherein each of the first sense amplifier drive line (Ln, Lp) is the unit (1A, 2A, 3A, 4A, 1B, 1B, 3B, 4B, 1C, 2C, 3C, 4C, 1D, 2D). And divided into a plurality of first unit sense amplifier drive lines L1n, L2n, L3n, L4n, L1p, L2p, L3p, L4p, corresponding to 3D and 4D, and the second sense amplifier drive lines SAN, SAP) A plurality of second unit sense amplifier drive lines SAN1A, respectively connected to the corresponding first unit sense amplifier drive lines L1n, L2n, L3n, L4n, L1p, L2p, L3p, L4p. SAN2A, SAN3A, SAN4A, SAN1B, SAN2B, SAN3B, SAN4B, SAN1C, SAN2C, SAN3C, SAN4C, SAN1D, SAN2D, SAN3D, SAN4D, SAP1A, SAP2A, SAP3A, SAP4A, SAP1B, SAP2B, SAP3B, SAP4B, SAP1C, SAP1C A semiconductor memory device characterized by being divided into SAP3C, SAP4C, SAP1D, SAP2D, SAP3D, and SAP4D. The method of claim 8, wherein the second unit sense amplifier drive lines SAN1A, SAN2A, SAN3A, SAN4A, ... SAP1A, SAP2A, SAP3A, SAP4A, ... are gate transistors Q ₁ , Q ₅ , Q ₉ , Q ₁₃ , Q ₁₇ , Q ₂₁ , Q ₂₅ , Q ₂₉ , ...) A semiconductor memory device characterized in that connected to the first and second power lines (Vss, Vcc). 10. The apparatus of claim 9, wherein the corresponding second unit sense amplifier drive lines SAN1A, SAN2A, SAN3A, SAN4A, ... SAP1A, SAP2A, SAP3A, SAP4A, ... in the same partition block A, B, C, D. The connected gate transistors Q ₁ , Q ₅ , Q ₉ , Q ₁₃ ,... Q ₁₇ , Q ₂₁ , Q ₂₅ , Q ₂₉ ,... Are controlled by the same control signal SENA, SEPA to divide the division. Wherein one of the blocks (A, B, C, D) is selected and the units (1A, 2A, 3A, 4A, ...) in the selected block (A) are selected at the same timing. 10. Connection to corresponding second unit sense amplifier drive lines SAN1A, SAN2A, SAN3A, SAN4A, ... SAP1A, SAP2A, SAP3A, SAP4A, ... in the same division block A, B, C, D. The gate transistors Q ₁ , Q ₅ , Q ₉ , Q ₁₃ ,... Q ₁₇ , Q ₂₁ , Q ₂₅ , Q ₂₉ ,..., One read signal SEN1A, SEP1A and the remaining reproduction signals ( Controlled by SEN2A, SEN3A, SEN4A, SEP1A, SEP2A, SEP3A, SEP4A), one unit (1A) including the memory cells to be read in one selected block (A) is read out at high speed, and the remainder in the selected block (A) is read. And the units (1B, 1C, 1D) are reproduced only at a different timing than the read operation. 12. The readout unit (SEN1A) has a higher voltage value than that of the reproduction signals (SEN2A, SEN3A, SEN4A), so that the read operation unit (1A) is driven quickly, and the regeneration operation units (2A, 3A). , 4A) is slowly driven. The method of claim ₁₁ , further comprising data bus lines (DB ₂ , DB ₃ ; ι ₁₂ , ι ₁₃ ) and the data latch circuit (DL), the data bus lines (DB ₂ , DB ₃ ; ι ₁₂ , ι) ₁₃ ) is connected between the sense amplifiers (SA) and the data latch circuit (DL). The first data bus lines DB _{2 of} claim 13, wherein the data bus lines are connected to the sensing amplifiers SA along a word line WL direction and are provided in the first wiring layer W ₁ . , DB ₃ ) and the corresponding first bus lines DB ₂ and DB ₃ and the data latch circuit DL along the bit line BL direction, and the second wiring layer W _2. A second data bus line (ι ₁₂ , ι ₁₃ ) installed in the semiconductor memory device. 14. The data latch line of claim ₁₃ , wherein the second data bus lines ι ₁₂ and ι ₁₃ are connected to the plurality of first data bus lines DB ₂ and DB ₃ via gate transistors 31 and 32. Connected to the circuit DL, and the gate transistors 31 and 32 are controlled by the selector 35, whereby one of the first data bus lines DB ₂ and DB ₃ is selected to provide the data. A semiconductor memory device characterized by being connected to a latch circuit (DL). The method of claim 13, wherein the first data buslines DB ₂ and DB ₃ are divided into a plurality of busline groups DB ₂₁ , DB ₂₃ ; DB ₃₁ , and DB ₃₂ . Ι ₁₂ , ι ₁₃ and the data latch circuit DL are installed in accordance with the divided bus line groups DB ₂₁ , DB ₂₃ ; DB ₃₁ , DB ₃₂ , and the second data bus lines ( ι ₁₂ , ι ₁₃ are connected to the corresponding busline groups DB ₂₁ , DB ₂₃ ; DB ₃₁ , DB ₃₂ and the data latch circuit DL via a switching circuit SW, And one of each of the busline groups (DB ₂₁ , DB ₂₃ ; DB ₃₁ , DB ₃₂ ) is selected and connected to the respective data latch circuits (DL). 2. The semiconductor memory device of claim 1, further comprising signal lines provided in the first wiring layer (W ₁ ) and the second wiring layer (W ₂ ). The method of claim 1, wherein the second sense amplifier drive line (6: ι ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ ; SAN, SAP) is provided between the memory cell portion and the peripheral circuit portion, and the connection conductor (7) a semiconductor memory device characterized in that it is connected to one of said first and second power lines (Vss, Vcc). 2. The semiconductor memory device according to claim 1, wherein each of the memory cells (MC) is composed of a stacked capacitor (5C) and a memory cell transistor (5T). In claim 1, wherein the memory cells (MC) and said sense amplifiers (SA) of the first wiring layer (W ₁₎ provided on said second wiring layer (W _2), the data bus lines (DB _2, DB ₃ ; ι ₁₂ , ι ₁₃ ), sense amplifier drive lines (ι ₃ , ι ₁ ; Ln, Lp; ι ₃₁ , ι ₄₁ ; ι ₃₂ , ι ₄₂ ; SAN, SAP) other signal lines and power lines ( A semiconductor memory device characterized by being used for installation of Vss, Vcc). A plurality of word lines WL; A plurality of bit lines BL intersecting the word lines WL

); The 1 word line WL and the 1 bit line BL,

A plurality of memory cells MC each connected between the plurality of memory cells; 1 pair of said bit lines BL,

A plurality of sense amplifiers SA connected respectively to First power line Vss; Second power supply line Vcc; And connected between the first and second power lines Vss and Vcc and the respective sensing amplifiers SA, and installed in a wiring layer on the memory cells MC and the sensing amplifiers SA. A semiconductor memory device characterized by a pair of sense amplifier drive layers (ι ₁₆ , ι ₁₇ ).

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