KR930007102A - Analog level output system - Google Patents

Analog level output system Download PDF

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Publication number
KR930007102A
KR930007102A KR1019910015469A KR910015469A KR930007102A KR 930007102 A KR930007102 A KR 930007102A KR 1019910015469 A KR1019910015469 A KR 1019910015469A KR 910015469 A KR910015469 A KR 910015469A KR 930007102 A KR930007102 A KR 930007102A
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KR
South Korea
Prior art keywords
analog level
conversion method
data conversion
output system
determining
Prior art date
Application number
KR1019910015469A
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Korean (ko)
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KR930009429B1 (en
Inventor
박도용
이혜경
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019910015469A priority Critical patent/KR930009429B1/en
Publication of KR930007102A publication Critical patent/KR930007102A/en
Application granted granted Critical
Publication of KR930009429B1 publication Critical patent/KR930009429B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

본 발명은 정보의 송, 수신에 관련된 교환기내 코덱(CODEC) IC에서 펄스부호변조데이타가 데이타 변환방식에 따라 다른 아날로그 값으로 디코딩되도록 아날로그 레벨을 조정하여 아날로그 레벨을 출력하는 아날로그 레벨 출력시스템에 관한 것으로, 변환방식에 따라 분리된 칩을 단일 칩상에 구현하여 사용자가 데이타 변환방식을 선택하여 사용할 수 있도록 로직 컨트롤부를 구성하여 데이타 변환방식에 호환환성을 부여하며, 칩의 활용성을 높일 수 있다.The present invention relates to an analog level output system for outputting an analog level by adjusting the analog level so that pulse code modulation data is decoded into different analog values according to a data conversion method in an intra-codec IC that is related to transmitting and receiving information. By implementing a separate chip according to a conversion method on a single chip, a logic control unit may be configured to allow a user to select and use a data conversion method, thereby providing compatibility with the data conversion method, and increasing chip utilization.

Description

아날로그 레벨 출력 시스템Analog level output system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 본 발명 아날로그 레벨 출력 시스템의 블록다이어그램,6 is a block diagram of an analog level output system of the present invention,

제7도는 본 발명 요부인 로직 컨트롤부의 일실시예,7 is an embodiment of a logic control unit that is an essential part of the present invention;

제8도는 본 발명에 따른 아날로그 레벨 결정소자 및 스위치부의 일실시예를 나타낸 회로도이다.8 is a circuit diagram showing an embodiment of an analog level determining element and a switch unit according to the present invention.

Claims (4)

데이타 변환방식을 결정하는 변환방식 컨트롤신호(1)와 PCM데이타(2)를 논 리적으로 조합하는 로직 컨트롤부(5)와, 상기 로직조정부(5)의 출력신호에 따라 온-오프 동작을 수행하는 컨트롤스위치(6)를 연결하고, 상기 컨트롤 스위치(6)의 온-오프에 따라 특정전압을 출력하는 아날로그 레벨 결정소자(3)가 연결됨을 특징으로 하는 아날로그 레벨 출력시스템.The logic control unit 5 logically combines the conversion method control signal 1 and the PCM data 2 for determining the data conversion method, and performs an on-off operation according to the output signal of the logic adjustment unit 5. And an analog level determining element (3) for outputting a specific voltage according to the on-off of the control switch (6). 제1항에 있어서, 상기 로직 컨트롤부(5)는 데이타 변환방식을 결정하는 컨트롤신호(11)와, PCM데이타(13) 및 초기치(12)를 논리조합하여 데이타 변환방식을 결정하는 것을 특징으로 하는 아날로그 레벨 출력시스템.2. The logic control unit according to claim 1, wherein the logic controller 5 logically combines the control signal 11 for determining the data conversion method, the PCM data 13 and the initial value 12, and determines the data conversion method. Analog level output system. 제1항에 있어서, 상기 컨트롤 스위치(6)를 데이타 변환방식을 결정하는 기능과 아날로그 레벨을 결정하는 기능을 수행할 수 있는 스위치로 구성함을 특징으로 하는 아날로그 레벨 출력시스템.The analog level output system according to claim 1, characterized in that the control switch (6) comprises a switch capable of determining a data conversion method and a function for determining an analog level. 제1항에 있어서, 상기 아날로그 레벨 결정소자(3)를 저항열을 이용하여 구성함을 특징으로 하는 아날로그 레벨 출력시스템.The analog level output system according to claim 1, characterized in that the analog level determining element (3) is configured using a resistor string. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910015469A 1991-09-04 1991-09-04 Analog level output system KR930009429B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910015469A KR930009429B1 (en) 1991-09-04 1991-09-04 Analog level output system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910015469A KR930009429B1 (en) 1991-09-04 1991-09-04 Analog level output system

Publications (2)

Publication Number Publication Date
KR930007102A true KR930007102A (en) 1993-04-22
KR930009429B1 KR930009429B1 (en) 1993-10-04

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ID=19319597

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015469A KR930009429B1 (en) 1991-09-04 1991-09-04 Analog level output system

Country Status (1)

Country Link
KR (1) KR930009429B1 (en)

Also Published As

Publication number Publication date
KR930009429B1 (en) 1993-10-04

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