KR930006976B1 - Semiconductor memory device - Google Patents

Abstract

The semiconductor element consists of active regions, word lines, bit lines, two MOSFETs which are formed on the active region, and source and drain. Active regions are formed lengthy in the bit line direction by removing field oxide with is formed between active regions. Word lines are formed lengthy with a width on active regions in the direction perpendicular to bit lines. Drain is formed on active region under both sides of word lines to contact bit lines. Source is formed on the exposed active region by removing the region in the middle of word line width, and is connected to electric charge storage electrodes. Common drains of two MOSFETs are connected to bit lines, and common sources are connected to one capacitor.

Description

Semiconductor memory device

1 is an equivalent circuit diagram of a conventional DRAM cell.

2 is a layout diagram in which predetermined regions of a conventional memory element are arranged.

3 is a cross-sectional view of the memory cell taken along the line AA ′ of FIG. 2.

4 is an equivalent circuit diagram of a DRAM cell according to the present invention.

5 is a layout diagram in which predetermined regions of a memory element of the present invention are arranged.

FIG. 6 is a cross-sectional view of the memory cell taken along line B-B 'of FIG.

FIG. 7 is a layout diagram in which a predetermined area of a memory element is arranged according to another embodiment of the present invention. FIG.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2, 2 ': field oxide film

3: gate oxide film 4A, 4B, 4C: word line

6A, 6B: Common source 8A, 8B, 8C: Charge storage electrode

9A, 9B, 9C: dielectric film 10: plate electrode

11, 11 ': Active Region 12, 12': Bitline

13A, 13B, 13C: Word line removal area 30A, 30B, 30B ', 30C: FET

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device. In particular, a thick field oxide film is formed between cells in a bit line direction while using a DRAM cell area having a conventional stack or trench capacitor structure as it is. The present invention relates to a semiconductor memory device comprising two transistors and one capacitor by forming transistors without forming them.

In general, an equivalent circuit of a DRAM cell composed of one transistor and one capacitor, as shown in FIG. 1, the gate of the field effect transistor (FET) Q1 is at the word line WL, and the drain of the FET Q1 is shown in FIG. The source of the FET Q1 on the silver bit line BL is connected to the capacitor C, and the other terminal of the capacitor is grounded or connected to the VCC / 2 terminal.

In order to highly integrate the structure of the DRAM cell on the silicon substrate, there are a fold bit line arrangement method and an open bit line arrangement method. Hereinafter, an open bit line arrangement method will be described. In addition, only the structure made before the formation of the capacitor of the bit line will be mentioned.

2 shows word lines 4A and 4B, bit lines 12 and 12 ', active regions 11 and 11', and capacitor charge storage electrodes 8A, 8B, 8A 'and 8B' by an open bit line arrangement method. ), And the portions other than the active regions 11 and 11 'are covered with a field oxide film.

3 is a cross-sectional view of a memory cell formed by cutting A-A 'of FIG. 2 and includes charge storage electrodes 8A and 8B and bit lines 12 and 12' on both sides of word lines 4A and 4B. Is formed, the charge storage electrodes 8A and 8B are connected to the respective sources 6A and 6B, the bit lines 12 and 12 'are connected to the common drain 6, and the charge storage electrodes 8A and 8B are connected to each other. It can be seen that the dielectric films 9A and 9B are formed on the upper part, and the plate electrode 10 is entirely coated on the structure.

In addition, the structure prevents leakage of charges stored in the charge storage electrodes 8A and 8B by forming field oxide films 2 and 2 'on both sides of the sources 6A and 6B, and prevents the active region and the active in the bit line direction. It insulates the regions, and by forming a field oxide film by LOCOS (Local Oxide Silicon) method, the active area is reduced by bird's beak phenomenon, and the field oxide film is formed during contact hole formation etching to contact the charge storage electrode with the source. The removal of Budvik can cause damage to the underlying silicon substrate and can also cause leakage currents.

Therefore, in order to solve the above problems, a memory device including two transistors and one capacitor is formed by forming another FET without forming a field oxide film formed between a conventional active region and an active region in the bit line direction. The purpose is to provide.

In addition, forming a FET between active and active has another object to improve the operating speed of the memory cell.

According to the present invention, an active region, a word line, and a bit line are arranged in an open bit line arrangement method, two MOSFETs are formed on the active region, a bit line is used for a common drain, and each source is A semiconductor memory device formed by connecting a charge storage electrode, wherein a field oxide film formed between an active region and an active region in the bit line direction is removed to form a long active region, and is orthogonal to the active region on the active region. A word line is formed to have a predetermined width in a direction, a predetermined region is removed in the middle of the word line width on the active region, a source is formed in the exposed active region, a charge storage electrode is connected, and active on both sides of the word line. A drain is formed in the region to contact the bit line, thereby reducing Two MOSFET drains are contacted to a bit line, and one capacitor is connected to two MOSFET common sources.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. 1 to 3 are referred to in the related art, so repeated descriptions thereof will be omitted. 4 is an equivalent circuit diagram of a new DRAM of the present invention, in which a FET is connected to a bit line BL and a word line WL like a conventional DRAM cell, and two FETs Q1 and Q2 are connected in parallel and two The capacitor C is connected to the sources of Q1 and Q2, and the operation speed can be increased by doubling the amount of current when storing or reading the charge in the capacitor C.

FIG. 5 is a layout diagram in which respective regions are arranged in order to form the equivalent circuit of FIG. 4 on the silicon substrate 1, and includes word lines 4A, 4B, 4B 'and 4C and bit lines 12 and 12. FIG. '), Active region 11, 11' capacitor charge storage electrodes 8A, 8B, 8C, 8A ', 8B', 8C 'and word line removal regions 13A, 13B, 13C, 13A', 13B ', 13C ') And so on.

FIG. 6 is a cross-sectional view of the memory cell formed by cutting the BB ′ of FIG. 5 according to the present invention, and the word lines 4A, 4B, and 4C for gate electrodes spaced at predetermined intervals on the silicon substrate 1. Is formed and the gate word lines 4B and 4B 'positioned at the left and right of the center charge storage electrode 8B are spaced apart in cross-sectional structure, but as shown in FIG. Is one word line 4B interconnected at the edge of the Nt, which is wide and serves as the word line for the gates of the two FETs 30B and 30B ', and at the same time two FETs Drives 30B and 30B '. The charge storage electrode 8B is connected to a common source 6A in the silicon substrate 1, and the bit lines 12 on the left and right sides of the charge storage electrode 8B are connected to the common drains 6 and 6 '. On the other side, word lines 4A and 4C are formed on the other side, so that the conventional field oxide film is eliminated and FETs 30A and 30C are formed, respectively.

A gate oxide film 3 is formed between the gate word lines 4A, 4B and 4C and the silicon substrate 1, and the word lines 4A, 4B and 4C and the charge storage electrodes 8A, 8B and 8C. Insulation layers 5 and 7 are formed between the bit lines 12, and the plate electrode 10 includes capacitor dielectric films 9A, 9B, and 9C on the charge storage electrodes 8A, 8B, and 8C. Is formed on the entire structure. Insulating each device in the bit line direction by using a word line instead of a thick field oxide film can double the effective channel width of the transistor to further improve the cell performance within the same cell area.

In general, since the amount of charge stored in the capacitor is almost unchanged, the small transistor has a low current driving capability and thus a long delay, and the width of the word line is close to the minimum line width. Increasing the resistance is a more serious problem. In the present invention, since the width of the word line is reduced, the resistance is shortened, and thus the delay time of the signal is shortened. These points are more effective because the size of the transistor decreases as the density of DRAM increases. have.

7 is a further embodiment of the present invention similarly to the fifth embodiment of the bit lines 12 and 12 ', active regions 11 and 11', charge storage electrodes (8A, 8B, 8C, 8A ', 8B', 8C ') is a layout in which the regions of word lines 4A, 4B, 4B', and 4C are arranged as shown in FIG. 2, but the word lines 4B and word lines 4B 'are interconnected at both ends. .

The operation of the memory cell formed as shown in FIG. 7 is the same as that of the present invention. As mentioned above, the present invention forms a transistor by making the insulation in the direction parallel to the bit line to be an active region without using a thick field oxide film, so there is no pud oxide film that insulates the bit line in parallel. The terminal is reduced by that amount.

In addition, Budvik in the bit line direction is eliminated, and Budvik in the word line direction forms a wide word line, so that the source connecting the charge storage electrode is reduced to Budvik to a minimum, thereby sufficiently securing the area of the active region. .

In addition, since the ion implantation is performed by tilting the substrate in order to prevent the junction depth from being deepened due to the channeling effect of impurities in the ion implantation process of forming the source and drain of the transistor, the source / drain region may be reduced. It is formed asymmetrically about the word line. In this case, the electrical properties appear asymmetrically. In the cell of the present invention, since two transistors are used in which the source / drain is changed, such a phenomenon is canceled with each other so that the above problem does not occur.

In addition, since the capacitor contact region is surrounded by the polycrystalline silicon used in the word line, this protects the Budvik portion of the oxide film in the word line direction during the dry etching process, thereby reducing the cause of leakage current.

Claims (2)

The active bit, the word line, and the bit line are arranged in an open bit line arrangement method, two MOSFETs are formed on the active area, a bit line is used for the common drain, and a charge storage electrode is used for each source. In a semiconductor memory device formed by connecting, a field oxide film formed between an active region and an active region in the bit line direction is removed to form an active region long, and a word line is formed on the active region in a direction orthogonal to the bit line. A predetermined width is formed, a drain is formed in the active regions under both sides of the word line, and a bit line is contacted, and a source is formed in the exposed active region by removing a predetermined region in the middle of the word line width on the active region. The charge storage electrode is connected, so that the drain of the MOSFET Is connected, the two MOSFET common source, the semiconductor memory device characterized in that the one capacitor is connected. The semiconductor memory device of claim 1, wherein two word lines each having a predetermined width are formed long and connected at an end thereof, instead of removing a predetermined region from an upper portion of the active region of the word line.