KR930006937A - Semiconductor Memory Chips with Porous Storage Electrodes - Google Patents

Semiconductor Memory Chips with Porous Storage Electrodes Download PDF

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Publication number
KR930006937A
KR930006937A KR1019910015286A KR910015286A KR930006937A KR 930006937 A KR930006937 A KR 930006937A KR 1019910015286 A KR1019910015286 A KR 1019910015286A KR 910015286 A KR910015286 A KR 910015286A KR 930006937 A KR930006937 A KR 930006937A
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KR
South Korea
Prior art keywords
storage node
dielectric layer
semiconductor memory
porous
capacitor
Prior art date
Application number
KR1019910015286A
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Korean (ko)
Other versions
KR950014808B1 (en
Inventor
진대제
박영우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910015286A priority Critical patent/KR950014808B1/en
Publication of KR930006937A publication Critical patent/KR930006937A/en
Application granted granted Critical
Publication of KR950014808B1 publication Critical patent/KR950014808B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

Abstract

본 발명은 제한된 영역에 형성되는 고용량 반도체 캐패시터에 관한 것으로써 작은 면적에 충분한 스토리지 캐패시턴스를 가지며 1트랜지스터 1캐패시터형의 다이나믹 랜덤 액세스 메모리쎌을 제공하기 위한 것으로써 반도체 기판상에 형성된 제1전극의 스토리지 노오드와 상기 스토리지 노오드상에 형성된 유전체층과 상기 유전체층상에 형성된 제2전극의 도체층으로 구성되는 캐패시터에 있어서 상기 스토리지 노오드가 다공질의 스토리지 노오드임을 특징으로 하는 캐패시터.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high capacity semiconductor capacitor formed in a limited region, which has sufficient storage capacitance in a small area, and provides a one-transistor, one-capacitor type dynamic random access memory 으로써 which is formed on a semiconductor substrate. A capacitor comprising a node, a dielectric layer formed on the storage node, and a conductor layer of a second electrode formed on the dielectric layer, wherein the storage node is a porous storage node.

Description

다공질 스토리지 전극을 가지는 반도체 메모리 쎌Semiconductor Memory Chips with Porous Storage Electrodes

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 다공질 스토리지 전극을 가지는 반도체 메모리 쎌의 공정도.2 is a process diagram of a semiconductor memory chip having a porous storage electrode according to the present invention.

Claims (3)

반도체 기판상에 형성된 제1전극의 스토리지 노오드와 상기 스토리지 노오드상에 형성된 유전체층과 상기 유전체층상에 형성된 제2전극의 도체층으로 구성되는 캐패시터에 있어서 상기 스토리지 노오드가 다공질의 스토리지 노오드 임을 특징으로 하는 캐패시터.In a capacitor comprising a storage node of a first electrode formed on a semiconductor substrate, a dielectric layer formed on the storage node, and a conductor layer of a second electrode formed on the dielectric layer, the storage node is a porous storage node. Capacitor characterized by the above-mentioned. 반도체 메모리 장치에서 사용하기 위한 메모리 쎌에 있어서 제1도전형의 반도체 기판상에 제1도전형과 반대되는 제2도전형의 소오스 및 드레인 영역과 이 영역 사이에 인접한 게이트 전극으로 구성되는 트랜스퍼 트랜지스터와, 상기 소오스 영역과 접촉하며 상기 게이트 전극과 절연되어 다공질화된 제1전극이 되는 스토리지 노오드와, 상기 다공질의 스토리지 노오드상에 도포된 유전체층과, 상기 유전체층상에 도포된 제2전극이 되는 도체층으로 구성됨을 특징으로 하는 반도체 메모리 쎌.A transfer transistor comprising a source and drain region of a second conductive type opposite to the first conductive type and a gate electrode adjacent to the region on a semiconductor substrate of the first conductive type in a memory cell for use in a semiconductor memory device; A storage node in contact with the source region and insulated from the gate electrode to become a porous first electrode, a dielectric layer coated on the porous storage node, and a second electrode coated on the dielectric layer A semiconductor memory comprising a conductor layer iii. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910015286A 1991-09-02 1991-09-02 Method of manufacturing a semiconductor memory cell having a storage node KR950014808B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910015286A KR950014808B1 (en) 1991-09-02 1991-09-02 Method of manufacturing a semiconductor memory cell having a storage node

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910015286A KR950014808B1 (en) 1991-09-02 1991-09-02 Method of manufacturing a semiconductor memory cell having a storage node

Publications (2)

Publication Number Publication Date
KR930006937A true KR930006937A (en) 1993-04-22
KR950014808B1 KR950014808B1 (en) 1995-12-15

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ID=19319481

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015286A KR950014808B1 (en) 1991-09-02 1991-09-02 Method of manufacturing a semiconductor memory cell having a storage node

Country Status (1)

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KR (1) KR950014808B1 (en)

Also Published As

Publication number Publication date
KR950014808B1 (en) 1995-12-15

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