KR930006931A - NAND type mask rom with virtual ground form - Google Patents

NAND type mask rom with virtual ground form Download PDF

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Publication number
KR930006931A
KR930006931A KR1019910016757A KR910016757A KR930006931A KR 930006931 A KR930006931 A KR 930006931A KR 1019910016757 A KR1019910016757 A KR 1019910016757A KR 910016757 A KR910016757 A KR 910016757A KR 930006931 A KR930006931 A KR 930006931A
Authority
KR
South Korea
Prior art keywords
transistors
bit line
mask rom
nand type
type mask
Prior art date
Application number
KR1019910016757A
Other languages
Korean (ko)
Other versions
KR950001836B1 (en
Inventor
김종오
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019910016757A priority Critical patent/KR950001836B1/en
Publication of KR930006931A publication Critical patent/KR930006931A/en
Application granted granted Critical
Publication of KR950001836B1 publication Critical patent/KR950001836B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

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  • Read Only Memory (AREA)

Abstract

본 발명은 가상접지 형태를 갖는 NAND형 마스크 롬에 관한 기술로, 한 개의 비트라인으로부터 4개의 스트링을 병렬접속하되, 2개의 스트링을 한조로하여 이웃하는 비트라인에 각기 접속한 다음, 이웃하는 비트라인에 비트라인 구동전압 VBIT을 공급하거나 또는 접지상태로하여 별도의 접지선을 제거한 가상접지 형태를 갖는 NAND형 마스크롬에 관해 기술된다.The present invention relates to a NAND type mask ROM having a virtual ground type, wherein four strings are connected in parallel from one bit line, and two strings are connected in pairs to neighboring bit lines, and then the neighboring bits are connected. A NAND type mask ROM having a virtual ground form in which a bit line driving voltage VBIT is supplied to a line or grounded is removed.

Description

가상접지 형태를 갖는 NAND형 마스크롬NAND type mask rom with virtual ground form

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 사용되는 NAND형 셀어레이의 구성도.3 is a block diagram of a NAND cell array used in the present invention.

Claims (1)

NAND형 마스크 롬에 있어서, 트랜지스터(Q101 및 Q102)를 각기 경유하여 우수차 비트라인(BL2 및 BL4)에 접속되어 비트라인에 구동전압을 공급하기 위한 비트라인 바이어스 회로(31)와, 상기 트랜지스터(Q101 및 Q102)의 게이트 단자로부터 접속되어 입력되는 어드레스 신호에 따라 상기 트랜지스터(Q101 및 Q102)를 선택적으로 동작시키기 위한 Y-디코더(32)와, 각각의 기수차 비트라인(BL1, BL3 및 BL5)에 병렬접속되되 자신의 게이트 단자에 입력되는 신호에 따라 자신의 비트라인에 접지 또는 비트라인 구동전압(VBIT)을 공급하는 한쌍의 트랜지스터(Q103 및 Q104, Q105 및 Q106, Q107 및 Q108)와, 상기 트랜지스터(Q103 내지 Q108)의 각 게이트 단자로부터 접속되고, 입력되는 어드레스 신호에 따라 이들 트랜지스터를 선택적으로 동작시키기 위한 접지 셀렉터(34)와, 비트라인간에 접속된 다수의 스트링(10 내지 17)에 스트링 선택신호 및 워드선 동작신호를 공급하기 위한 X-디코더(33)로 구성되는 것을 특징으로 하는 가상접지 형태를 갖는 NAND형 마스크롬.In the NAND type mask ROM, a bit line bias circuit 31 for supplying a driving voltage to the bit line by connecting to the even-order bit lines BL2 and BL4 via the transistors Q101 and Q102, respectively, and the transistor ( Y-decoder 32 for selectively operating the transistors Q101 and Q102 in accordance with an address signal connected and input from the gate terminals of Q101 and Q102, and respective aberration bit lines BL1, BL3 and BL5. A pair of transistors (Q103 and Q104, Q105 and Q106, Q107 and Q108) connected in parallel to and supplying the ground or bit line driving voltage (VBIT) to its bit line according to a signal input to its gate terminal, A ground selector 34 connected from each gate terminal of the transistors Q103 to Q108 for selectively operating these transistors in accordance with an input address signal, and a connection between the bit lines And an X-decoder (33) for supplying a string selection signal and a word line operation signal to the plurality of strings (10 to 17). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016757A 1991-09-26 1991-09-26 Nand type mask rom with virtual ground KR950001836B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910016757A KR950001836B1 (en) 1991-09-26 1991-09-26 Nand type mask rom with virtual ground

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910016757A KR950001836B1 (en) 1991-09-26 1991-09-26 Nand type mask rom with virtual ground

Publications (2)

Publication Number Publication Date
KR930006931A true KR930006931A (en) 1993-04-22
KR950001836B1 KR950001836B1 (en) 1995-03-03

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ID=19320354

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910016757A KR950001836B1 (en) 1991-09-26 1991-09-26 Nand type mask rom with virtual ground

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KR (1) KR950001836B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100358148B1 (en) * 1995-05-15 2003-01-08 주식회사 하이닉스반도체 Mask rom
KR100358139B1 (en) * 1995-07-11 2003-01-15 주식회사 하이닉스반도체 Mask rom
KR100572622B1 (en) * 2004-12-22 2006-04-24 삼성전자주식회사 Multi-time programmable semiconductor memory device and multi-time programming method for the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100358148B1 (en) * 1995-05-15 2003-01-08 주식회사 하이닉스반도체 Mask rom
KR100358139B1 (en) * 1995-07-11 2003-01-15 주식회사 하이닉스반도체 Mask rom
KR100572622B1 (en) * 2004-12-22 2006-04-24 삼성전자주식회사 Multi-time programmable semiconductor memory device and multi-time programming method for the same

Also Published As

Publication number Publication date
KR950001836B1 (en) 1995-03-03

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