KR930004909Y1 - Generator for time information - Google Patents

Abstract

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Description

Time information generation circuit

1 is a block diagram showing a schematic configuration of the present invention.

2 is a timing diagram showing the operation of the time information generator of the present invention.

Figure 3 is a block diagram showing the configuration of the present invention.

4 is a block diagram showing a detailed configuration of the present invention.

5 is a waveform diagram showing the operation of the present invention.

* Explanation of symbols for main parts of the drawings

3: Bus Clock Generator 7: TTLIC

5, 5a, ..., 5n, 6, 6a, ..., 6n: Time information generator 10: Latch

9: delay element 11: buffer

The present invention relates to a time information generation circuit that is a reference for bus operation in a multiprocessor system using a synchronous bus.

In the related art, when the transmission speed for transmitting data on a synchronous bus is increased, that is, when the bus clock frequency of the bus is increased, there is a problem that the length of the bus causes an insignificant serious problem of delaying signal transmission. .

As the above problems, i.e., the signal propagation delay increases, the performance of the system is degraded. Therefore, information for precisely controlling the operation of the bus on each board is needed.

In order to accurately operate the bus, the time that is the reference of the bus operation, that is, reference time information, is required.

Accordingly, the present invention aims to provide a more improved system by providing a time information generation circuit that provides accurate bus operation in a processor and a memory.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows a schematic configuration of the present invention, in which a plurality of processors (1, 1a, ..., 1n) share a plurality of memories (2, 2a, ..., 2n) through a system bus (4). In a multiprocessor system, a bus clock generator (3) for supplying a bus clock for an operating cycle of the system, the processors (1, 1a, ..., 1n) and the memory (2, 2a, ... (2,5n) and time information generator (TPG: Time pulse generator (TPG) (5,5a, ..., 5n), (6,6a, ..) which outputs reference time information under the control of the bus output generator (3). ., 6n).

2 shows an operation state of the time information generator. The time information generators 5, 5a, ..., 5n which receive a bus clock having a period of 80 n sec from the clock generator 3 via the system bus 4 are shown in FIG. In (6,6a, ..., 6n), the time information (TP0, TP10, TP20, ..., TP60, TP70, with a delay time of 10n sec and a pulse width of 20n sec) Occurs.

3 shows the configuration of the time information generator. From the bus clock generator 3, the bus clock bclk passes through the transistor transistor logic integrated crtrcuit (TTLIC) 7 and passes through the NAND gate 8 to the delay element 9. After a certain time delay at), the output of continuous pulses from the delay element 9 is delayed by 10 n sec while passing through the latch 10 and the buffer 12, and time information having a pulse width of 20 n sec. Get the output.

4 shows a detailed configuration. In TTLIC (7) where the bus clocks bclk9 to bclk0 are applied to the input terminals D9 to D0 from the bus clock generator 3, 5n sec. To the output terminals Q9 to Q0 due to the characteristics of the device. The delayed pulse is applied to the input terminal of the NAND gate 8 and the output delayed 5n sec to the NAND gate 8 is applied to the input terminal IN of the delay element 9, regardless of the delay of this time information. A predetermined time is delayed in the operation of the system, and outputted as a continuous pulse (C2, C3, C4, C5, C6, C7, C0, C1) to the output terminals (Q1) to (Q8).

The pulses C7, C0, C1, C2, C3, C4, C5 and C6 of the delay element 9 are applied to the clock terminals of the latches 10a to 10h, respectively, and the output terminal Q of the latch 10a is applied. In this case, the time information signal is passed through the buffer 11a while being applied to the input terminal D of the latch C1. Output at the same time Outputs the time information signal tp0 via the buffer 11b while being applied to the clear terminal CL of the latch 10g, and latches 10b, 10c, 10d, 10e, and 10f. At the output terminal Q of the), the buffers 11c, 11f, 11h, and 11j are connected to the input terminals D of the latches 10d, 10e, 10f, 10g, and 10h. ), Time signal through (11p) And the time information is output from the output terminals Q of the latches 10g and 10h through the buffers 10n and 11p. And the output terminal of the latches 10b to 10h. Is connected to the clear terminals CL of the latches 10h, 10a, 10b, 10c, 10d, 10e, and 10f, and the buffers 11d, 11e, and 11g respectively. The time information signals tp1, tp2, tp3, tp4, tp5, tp6 and tp7 are respectively passed through, (11i), (11k), (11n) and (11o). Output

Therefore, according to the time information generator of the present invention, the bus clocks bclk9 to bclk0 shown in FIG. 5e from the bus clock generator 3 pass through the TTLIC 7 and the NAND gate 8 to the same clock as in FIG. 5b. Continuous pulse (C2) sequentially delayed by 10n sec such as 5c, ca, cb, ..., dn degrees from the output terminals (Q1) to (Q8) to be input to the input terminal (IN) of the delay element (9) , (C3), (C4), (C5), (C6), (C7), (C0), and (C1) to be applied to the clock stages of the latches (10a) to (10h).

And the two output terminals Q of the latches 10a to 10h, The signals output from are delayed by 10n sec as shown in Figs. 5d, da through buffers 11a through 11p while the input terminal D is input to the clear terminal CL with 20n sec delayed. Time information signal (tp0) to (tp7), which has a pulse width of 20n sec and is a period of 80n sec, It can be seen that the bus operation of the processor and the memory in which each time information generator exists is corrected by the time information signal.

Claims (1)

The TTLIC (7) and the NAND gate (8) to delay the bus clock from the bus clock generator (3) 10n sec, and has a delay time of 10n sec for the signal via the NAND gate (8) A delay element 9 for outputting continuous pulses C2, C3, C4, C5, C6, C7, C0, C1, and the delay element 9 Time information signals (tp0) to (tp9) having pulse widths of 20 n sec, with continuous pulses C0 to C7 from And latches (10a) to (10b) for outputting through the buffers (11a) to (11p).