KR930004762Y1 - Stabilizing circuit of oscillator - Google Patents
Stabilizing circuit of oscillator Download PDFInfo
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- KR930004762Y1 KR930004762Y1 KR2019910000673U KR910000673U KR930004762Y1 KR 930004762 Y1 KR930004762 Y1 KR 930004762Y1 KR 2019910000673 U KR2019910000673 U KR 2019910000673U KR 910000673 U KR910000673 U KR 910000673U KR 930004762 Y1 KR930004762 Y1 KR 930004762Y1
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- 230000000087 stabilizing effect Effects 0.000 title description 2
- 230000010355 oscillation Effects 0.000 claims description 49
- 239000003990 capacitor Substances 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 11
- 230000006641 stabilisation Effects 0.000 claims description 7
- 238000011105 stabilization Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 8
- 230000010365 information processing Effects 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
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- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 발명에 따른 발진주파수 안정화회로의 일실시예의 회로도이다.1 is a circuit diagram of an embodiment of an oscillation frequency stabilization circuit according to the present invention.
제2도는 제1도에 도시된 회로의 각 부분에서 출력되는 파형을 도시한 출력파형도이다.FIG. 2 is an output waveform diagram showing waveforms output from each part of the circuit shown in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 수정발진자 20,21 : 제1,2클럭발생기10: crystal oscillator 20,21: first and second clock generator
30 : 배타적 논리합소자 40 : 적분회로30: exclusive logic element 40: integrating circuit
50 : 디지탈회로 60 : 발전회로50: digital circuit 60: power generation circuit
R1∼R5 : 저항 C1,C3,C5 : 콘덴서R1 to R5: resistors C1, C3, C5: capacitors
C2 : 가변콘덴서 VC1 : 바렉터다이오드C2: Variable Capacitor VC1: Varactor Diode
본 고안은 소정 주파수의 발진신호를 발생하는 발진회로에 관한 것으로, 특히 외부 영향에 의해 변화되는 발진주파수를 안정화시키는 발진주파수 안정화회로에 관한 것이다.The present invention relates to an oscillation circuit for generating an oscillation signal of a predetermined frequency, and more particularly, to an oscillation frequency stabilization circuit for stabilizing an oscillation frequency changed by an external influence.
일반적인 발진회로는 송수신장치나 디지탈 정보처리장치를 비롯하여 각종 동기식 제어회로 등에 회로를 인터페이스시키고자 할 때 사용되어 시스템이 요구하는 주파수의 발진신호를 제공할 목적으로 사용된다.A general oscillation circuit is used to interface circuits to various synchronous control circuits such as a transmission / reception device or a digital information processing device, and to provide an oscillation signal of a frequency required by the system.
그러나, 종래에 사용되었던 발진회로는 수정발진기를 사용하여 목적시스템이 요구하는 주파수의 발진신호를 공급하였는데, 만약 주변의 환경의 변화에 의하여 발생되는 발진신호가 영향을 받아서 변화되면 전송되는 정보의 분리가 불가능하거나 원래의 신호를 얻을 수 없으며 또한 정보처리중 각종 오류가 발생되는 문제점을 가지고 있었다.However, the oscillation circuit used in the prior art uses a crystal oscillator to supply the oscillation signal of the frequency required by the target system. If the oscillation signal generated by the change of the surrounding environment is affected and separated, the information transmitted is separated. Was not possible or could not get the original signal and also had various problems during the information processing.
즉, 종래의 발진회로내의 수정발진자는 주위의 온도 및 자계 등과 같은 외부영향에 의해 발진신호의 발진주파수가 변동된다. 이로 인하여 발진회로를 사용하는 시스템이 변동되는 발진신호에 의해 오동작을 하게 되었다.In other words, the crystal oscillator in the conventional oscillation circuit varies the oscillation frequency of the oscillation signal due to external influences such as ambient temperature and magnetic field. This causes the system using the oscillation circuit to malfunction due to fluctuating oscillation signals.
따라서 본 고안의 목적은 발진회로의 발진주파수를 안정화시킬 수 있는 발진주파수 안정화회로를 제공하는 것이다.Therefore, an object of the present invention is to provide an oscillation frequency stabilization circuit that can stabilize the oscillation frequency of the oscillation circuit.
상기 목적을 달성하기 위하여, 본 고안은 각기 클럭을 가지는 다수의 디지탈회로; 상기 디지탈회로로 부터의 클록신호를 배타적 논리합연산을 하기 위한 배타적논리합소자; 배타적 논리합연산된 신호를 적분하여 DC화하기 위한 적분회로; 상기 적분회로로부터 인가되는 DC전압 레벨에 따라 용량값에 변화시켜 발진신호의 발진주파수를 결정하는 발진회로를 포함하여 상기 발진회로는 전원 및 접지전원사이에 직렬접속된 수정발진자 및 제1콘덴서; 상기 직렬접속된 수정발진자 및 제1콘덴서에 병렬접속된 제2콘덴서; 상기 제2콘덴서에 병렬접속된 제어용 가변용량기를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises a plurality of digital circuits each having a clock; An exclusive logic sum element for performing exclusive logic operation on the clock signal from the digital circuit; An integrating circuit for integrating the exclusive logic-operated signal into DC; The oscillation circuit includes a crystal oscillator and a first capacitor connected in series between a power supply and a ground power supply, including an oscillation circuit which determines an oscillation frequency of an oscillation signal by varying a capacitance value according to a DC voltage level applied from the integrating circuit; A second capacitor connected in parallel to the series connected crystal oscillator and the first capacitor; And a control variable capacitor connected in parallel to the second capacitor.
이하 본 고안을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 고안에 따른 실시예의 발진주파수 안정화회로의 회로도이다.1 is a circuit diagram of an oscillation frequency stabilization circuit of an embodiment according to the present invention.
제1도에 있어서, 50은 접속되는 디지탈회로를 블록으로 표시한 것으로 본 고안에서는 일예로서 디지탈1(20)과 디지탈2(21)가 접속되는 경우를 도시하였고, 30은 배타적논리합소자, 40은 입력신호를 적분하는 적분회로이고, 60은 발진회로이다.In FIG. 1, 50 denotes a digital circuit to be connected as a block. In the present invention, an example in which digital 1 (20) and digital 2 (21) are connected is shown, 30 is an exclusive logic element, and 40 is an example. An integration circuit for integrating the input signal and 60 is an oscillation circuit.
상기와 같은 구성은 보다 세분하여 상세하게 살펴보면 다음과 같다.The configuration as described above is described in more detail as follows.
발진회로(60)은 공급전원(Vcc)과 출력단자(5) 사이에 접속되는 수정발진자(10), 출력단자(5)와 접지전원(GND) 사이에 접속되며 동시에 수정발진자(10)와 직렬로 접속되는 콘덴서(C1), 공급전원(B+) 및 접지전원(GND) 사이에 접속되며, 직렬로 접속되는 수정발진자(10)와, 콘덴서(C1)에 대하여 병렬로 접속되는 가변콘덴서(C2), 공급전원(B+)과 접지전원(GND) 사이에 직렬로 접속되는 콘덴서(C3)와 바렉터 다이오드(VC1) 및 콘덴서(C3)와 바렉터다이오드(VC1) 사이의 접점에 연결되는 저항(R8)으로 이루어진다.The oscillation circuit 60 is connected between the crystal oscillator 10 and the output terminal 5 and the ground power supply GND connected between the supply power supply Vcc and the output terminal 5, and are in series with the crystal oscillator 10. Is connected between the capacitor C1, the supply power source B + and the ground power source GND connected to each other, the crystal oscillator 10 connected in series, and the variable capacitor C2 connected in parallel to the capacitor C1. , A resistor R8 connected to the capacitor C3 and the selector diode VC1 and the contact between the capacitor C3 and the selector diode VC1 connected in series between the supply power supply B + and the ground power supply GND. )
이때 바렉터다이오드(VC1)의 캐소우드는 콘덴서(C3)에 애노우드는 접지전원(GND)에 결합된다.At this time, the cathode of the varactor diode VC1 is coupled to the capacitor C3 and the anode is coupled to the ground power source GND.
그리고 적분회로(40)는 5개의 저항(R1∼R5), 두 개의 콘덴서(C4,C5) 및 하나의 연산증폭기(A1)로 구성되어 입력신호를 적분하여 DC화한다. 즉, 입력신호를 적분하여 평균화하는 역할을 하는 것이다.The integrating circuit 40 is composed of five resistors R1 to R5, two capacitors C4 and C5, and one operational amplifier A1 to integrate the input signal into DC. In other words, it integrates and averages the input signal.
디지탈회로(50)에서의 디지탈1(20)에서 발생되는 클럭신호는 배타적논리합소자(30)의 제1입력단자로 입력된다. 디지탈2(21)에서 발생되는 클럭신호는 배타적논리합소자(30)의 제2입력단자로 입력된다. 배타적논리합소자(30)의 출력단자는 적분회로(40)의 입력단자에 접속된다.The clock signal generated by the digital 1 (20) in the digital circuit 50 is input to the first input terminal of the exclusive logic element 30. The clock signal generated in the digital 2 21 is input to the second input terminal of the exclusive logic element 30. The output terminal of the exclusive logic element 30 is connected to the input terminal of the integrating circuit 40.
적분회로(40)의 출력단자는 발진회로(60)의 입력단자에 접속되며 저항(R8)을 통하여 바렉터다이오드(VC1)의 캐소우드에 접속된다.The output terminal of the integrating circuit 40 is connected to the input terminal of the oscillating circuit 60 and is connected to the cathode of the selector diode VC1 through the resistor R8.
제2도는 제도에 도시된 회로의 각 부분에서 출력되는 파형을 도시한 출력파형도이다.2 is an output waveform diagram showing waveforms output from each part of the circuit shown in the drawing.
제2도에 있어서, 100은 디지탈1(20)에서 발생되는 클럭의 출력파형도, 101은 디지탈2(21)에서 발생되는 클럭의 출력파형도, 102는 배타적논리합소자(30)의 출력파형도이다.In FIG. 2, 100 is an output waveform diagram of a clock generated by digital 1 (20), 101 is an output waveform diagram of a clock generated by digital 2 (21), and 102 is an output waveform diagram of an exclusive logic element 30. to be.
제1도의 동작을 제2도에 도시된 파형도를 참조하여 설명한다.The operation of FIG. 1 will be described with reference to the waveform diagram shown in FIG.
디지탈회로(50)내의 디지탈1(20)에서는 제2도의 100으로 도시된 바와같은 소정 주파수의 제1발진신호를 발생하고 디지탈2(21)는 디지탈1(20)에서 발생되는 출력발진주파수와 동일한 제2발진신호를 발생하며 이 신호는 제2도 101과 같다. 여기서 제1발진신호는 제2발진신호보다 90°정도 위상이 앞선다.Digital 1 (20) in digital circuit (50) generates a first oscillation signal of a predetermined frequency as shown at 100 in FIG. 2, and digital 2 (21) is the same as the output oscillation frequency generated in digital 1 (20). A second oscillation signal is generated, which is shown in FIG. 101. Here, the first oscillation signal is about 90 degrees out of phase with the second oscillation signal.
배타적논리합소자(30)는 제1발진신호와 제2발진신호를 배타적 논리합연산하여 제2도 102와 같이 합성된 발진신호를 발생한다.The exclusive logical sum device 30 performs an exclusive logical operation on the first oscillation signal and the second oscillation signal to generate the synthesized oscillation signal as shown in FIG.
5개의 저항(R1∼R5) 및 2개의 콘덴서(C4,C5)와 하나의 연산증폭기(A1)로 이루어진 적분회로(40)는 저항(R1)과 콘덴서(C5)에 의해 결정되는 시정수에 따라 합성된 발진신호를 적분한다.The integrating circuit 40, which consists of five resistors R1 to R5, two capacitors C4 and C5 and one operational amplifier A1, depends on the time constant determined by the resistor R1 and the capacitor C5. Integrate the synthesized oscillation signal.
적분된 신호는 적분회로(40)의 출력단에 접속되는 발진회로(60) 내의 저항(R8)을 통하여 바렉터다이오드(VC1)의 캐소우드에 공급된다.The integrated signal is supplied to the cathode of the selector diode VC1 through the resistor R8 in the oscillating circuit 60 connected to the output terminal of the integrating circuit 40.
이때 적분된 신호는 4개의 저항(R1∼R4) 및 콘덴서(C5)에 의하여 결정된 증폭율만큼 증폭된다. 그리고 적분된 신호는 합성된 발진신호의 주파수가 변동됨에 따라 레벨값이 적응적으로 증가 또는 감소된다.At this time, the integrated signal is amplified by the amplification factor determined by the four resistors R1 to R4 and the condenser C5. The integrated signal adaptively increases or decreases the level value as the frequency of the synthesized oscillation signal changes.
바렉터다이오드(VC1)는 적분된 신호의 레벨값의 변화에 따라 용량값이 변환된다. 결국 바렉터다이오드(VC1)의 용량값은 주위 온도에 따라 적분된 신호에 의해 조절된다.The selector diode VC1 converts the capacitance value according to the change in the level value of the integrated signal. As a result, the capacitance value of the selector diode VC1 is adjusted by the integrated signal according to the ambient temperature.
가변콘덴서(C2)는 출력단자(5)상에 발생되는 발진신호의 발진주파수를 결정하기 위한 것이며, 사용자나 제작자에 의해 조절된다.The variable capacitor C2 is for determining the oscillation frequency of the oscillation signal generated on the output terminal 5 and is controlled by the user or the manufacturer.
수정발진자(10)는 콘덴서(C1)의 용량값과, 가변콘덴서(C2), 콘덴서(C3) 및 바렉터다이오드(VC1)의 병렬 합성용량 및 자체의 리액턴스값에 따른 공진주파수로 발진하여 발생되는 정현파 형태의 발진신호로 출력단자(5)를 송출한다.The crystal oscillator 10 is generated by oscillating at the resonance frequency according to the capacitance value of the capacitor C1, the parallel composite capacitance of the variable capacitor C2, the capacitor C3 and the varactor diode VC1, and the reactance value thereof. The output terminal 5 is sent as an oscillation signal in the form of a sine wave.
출력단자는 송수신기의 경우 혼합기, 디지탈 정보처리장치의 경우는 파형정형부를 통해 프로세서, 그리고 동기식 제어장치의 파형정형부를 통해 동기화 회로 등에 접속될 수 있다.The output terminal can be connected to a mixer through a mixer for a transceiver, a waveform through a waveform shaping unit for a digital information processing device, and a synchronization circuit through a waveform shaping unit of a synchronous control device.
상술한 바와같이 본 고안은 수정발진자를 포함하는 적어도 1개 이상의 별도의 발진기의 출력발진신호의 주위영향에 따른 발진신호의 변동폭을 감지하여 메인발진기의 리액턴스를 조절하여 원하는 주파수의 발진신호를 안정하게 공급할 수 있는 이점이 있다.As described above, the present invention detects the fluctuation of the oscillation signal according to the ambient influence of the output oscillation signal of at least one separate oscillator including the crystal oscillator, and adjusts the reactance of the main oscillator to stabilize the oscillation signal of the desired frequency. There is an advantage to supply.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910000673U KR930004762Y1 (en) | 1991-01-17 | 1991-01-17 | Stabilizing circuit of oscillator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910000673U KR930004762Y1 (en) | 1991-01-17 | 1991-01-17 | Stabilizing circuit of oscillator |
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| KR920015893U KR920015893U (en) | 1992-08-17 |
| KR930004762Y1 true KR930004762Y1 (en) | 1993-07-23 |
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| KR2019910000673U KR930004762Y1 (en) | 1991-01-17 | 1991-01-17 | Stabilizing circuit of oscillator |
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1991
- 1991-01-17 KR KR2019910000673U patent/KR930004762Y1/en not_active IP Right Cessation
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