KR930003566A - A / D conversion circuit with error detection - Google Patents

A / D conversion circuit with error detection Download PDF

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Publication number
KR930003566A
KR930003566A KR1019910012245A KR910012245A KR930003566A KR 930003566 A KR930003566 A KR 930003566A KR 1019910012245 A KR1019910012245 A KR 1019910012245A KR 910012245 A KR910012245 A KR 910012245A KR 930003566 A KR930003566 A KR 930003566A
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KR
South Korea
Prior art keywords
output
input terminal
encoder
bits
error detection
Prior art date
Application number
KR1019910012245A
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Korean (ko)
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KR930007651B1 (en
Inventor
조연형
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019910012245A priority Critical patent/KR930007651B1/en
Publication of KR930003566A publication Critical patent/KR930003566A/en
Application granted granted Critical
Publication of KR930007651B1 publication Critical patent/KR930007651B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

내용 없음.No content.

Description

에러 검출 기능을 갖는 A/D 변환회로A / D conversion circuit with error detection

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 에러 검출 기능을 갖는 A/D변환회로도.3 is an A / D conversion circuit diagram having an error detection function according to the present invention.

Claims (1)

아날로그 신호를 상위 N비트, 하위 M비트의 디지탈 신호로 변환하는 A/D변환회로에 있어서, 전원 전압(VRT-VRB)사이에 2N개의 저항(Rl-R4)을 직렬 연결하고 각 저항(R1-R4)의 공통 접속점의 전압을 코스 비교기(CCP1-CCP3)의 일측 입력단자에 기준전압으로 각기 입력하며 상기 코스 비교기(CCP1 -CCP3)의 타측 입력단자에는 아날로그 전압(Vin)을 인가하여 상기 코스 비교기(CCP1-CCP3)의 출력을 코스 엔코더(10)에 인가하여 디지탈 신호의 상위 비트(D2, D3)를 구성하고 상기 저항(Rl-R4)의 각각에 직렬로 연걸한 2N개의 저항(Rll-R44)을 병렬 접속하여 상기 코스 엔코더(10)의 제어 출력 신호(CLT1-CLT4)에 따라 상기 저항(Rl-R4)에 병렬 접속한 저항 스트링(Rll-R44)에서 특정 저항 스트링의 각 접속점 전압을 파인 비교기(FCP1-FCP3)와 일측 입력단자에서 인가하고 그 타측 입력단자에는 아날로그 신호(Vin)를 입력하며 그 출력을 파인 엔코더(12)에 입력하여 디지탈 출력의 하위 비트(D0, Dl)를 출력하게 하고 에러 검출 비교기(ECP1, ECP2)의 일측 입력단자에 상기 저항(Rl-R4)의 공통 접속점의 전압을 인가하고 그 타측에 아날로그 입력신호(Vin)를 인가하며 그 출력을 상기 파인 엔코더(12)로 입력하여 구성한 것을 특징으로 하는 에러 검출 기능을 갖는 A/D변환회로.In the A / D conversion circuit for converting analog signals into digital signals of upper N bits and lower M bits, 2 N resistors (Rl-R4) are connected in series between the supply voltages (V RT -V RB ), and each resistor The voltages of the common connection points of (R1-R4) are respectively input to one input terminal of the coarse comparators (CCP1-CCP3) as reference voltages, and an analog voltage (Vin) is applied to the other input terminals of the coarse comparators (CCP1 -CCP3). the course comparator upper bits (D2, D3) the configuration and the resistor (Rl-R4) 2 N resistors one yeongeol in series to each of the digital signals by applying the output of the (CCP1-CCP3) the course encoder 10 Each of the specific resistance strings in the resistance strings Rll-R44 connected in parallel with each other in parallel to the resistors Rl-R4 according to the control output signals CLT1-CLT4 of the coarse encoder 10 by connecting Rll-R44 in parallel. The connection point voltage is applied at the fine comparators (FCP1-FCP3) and one input terminal and the other input terminal is Inputs the analog signal Vin and inputs the output thereof to the fine encoder 12 to output the lower bits D0 and Dl of the digital output, and to the input terminal of one side of the error detection comparator ECP1 and ECP2. A / D conversion having an error detection function characterized by applying the voltage of the common connection point of Rl-R4, and applying the analog input signal Vin to the other side and inputting the output to the fine encoder 12. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910012245A 1991-07-18 1991-07-18 A/d converter with error detect means KR930007651B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910012245A KR930007651B1 (en) 1991-07-18 1991-07-18 A/d converter with error detect means

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910012245A KR930007651B1 (en) 1991-07-18 1991-07-18 A/d converter with error detect means

Publications (2)

Publication Number Publication Date
KR930003566A true KR930003566A (en) 1993-02-24
KR930007651B1 KR930007651B1 (en) 1993-08-14

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ID=19317417

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910012245A KR930007651B1 (en) 1991-07-18 1991-07-18 A/d converter with error detect means

Country Status (1)

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KR (1) KR930007651B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425309B1 (en) * 2001-11-22 2004-03-30 삼성전자주식회사 Apparatus for improving image quality

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425309B1 (en) * 2001-11-22 2004-03-30 삼성전자주식회사 Apparatus for improving image quality

Also Published As

Publication number Publication date
KR930007651B1 (en) 1993-08-14

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