KR930002877A - Method for manufacturing conductive layer pattern without step - Google Patents
Method for manufacturing conductive layer pattern without step Download PDFInfo
- Publication number
- KR930002877A KR930002877A KR1019910011474A KR910011474A KR930002877A KR 930002877 A KR930002877 A KR 930002877A KR 1019910011474 A KR1019910011474 A KR 1019910011474A KR 910011474 A KR910011474 A KR 910011474A KR 930002877 A KR930002877 A KR 930002877A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layer
- layer pattern
- mask
- groove
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음.No content.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 단차가 발생된 다층구조의 도전층 패턴을 도시한 단면도.1 is a cross-sectional view showing a conductive layer pattern of a multilayer structure in which a step is generated.
제3도는 본 발명의 제1실시예의 도전층 패턴을 도시한 레이아웃트도.3 is a layout diagram showing a conductive layer pattern of the first embodiment of the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930002877A true KR930002877A (en) | 1993-02-23 |
KR940005609B1 KR940005609B1 (en) | 1994-06-21 |
Family
ID=19316866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910011474A KR940005609B1 (en) | 1991-07-08 | 1991-07-08 | Method of making pattern |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940005609B1 (en) |
-
1991
- 1991-07-08 KR KR1019910011474A patent/KR940005609B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940005609B1 (en) | 1994-06-21 |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040331 Year of fee payment: 11 |
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LAPS | Lapse due to unpaid annual fee |