KR930002747B1 - Emergency protective circuit - Google Patents

Emergency protective circuit Download PDF

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Publication number
KR930002747B1
KR930002747B1 KR1019900006812A KR900006812A KR930002747B1 KR 930002747 B1 KR930002747 B1 KR 930002747B1 KR 1019900006812 A KR1019900006812 A KR 1019900006812A KR 900006812 A KR900006812 A KR 900006812A KR 930002747 B1 KR930002747 B1 KR 930002747B1
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KR
South Korea
Prior art keywords
circuit
nand gate
flip
capacitor
output
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KR1019900006812A
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Korean (ko)
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KR910021029A (en
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김종환
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삼화기연주식회사
김인석
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Priority to KR1019900006812A priority Critical patent/KR930002747B1/en
Publication of KR910021029A publication Critical patent/KR910021029A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Protection Of Static Devices (AREA)

Abstract

The detection circuit uses a phase separation circuit to remove th malfunction upon interrupting of electric power. The detection circuit comprises a RS flip-flop having NAND gates (G1,G2,G3), filters (M1,M2,M3) for applying three-phase signal to the RS flip- flop, the gate output (V) being charged in a capacitor (C1) through a diode (D), the gate output (W) being applied to a transistor (Q1) to prevent the capacitor operation, and a NAND gate (G4).

Description

역상 검출회로Reverse Phase Detection Circuit

제 1 도는 본 발명을 설명키 위한 실시예의 회로도1 is a circuit diagram of an embodiment for explaining the present invention.

제 2 도는 제 1 도 주요부분의 전압파형도이다.2 is a voltage waveform diagram of the main part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

RㆍSㆍT : 삼상전원연결단자 M1, M2, M3: 필터회로R, S, T: Three-phase power connection terminals M 1 , M 2 , M 3 : Filter circuit

M4: 정전압공급회로 G1, G2, G3: 3단 RS플립플롭M 4 : Constant voltage supply circuit G 1 , G 2 , G 3 : 3-stage RS flip-flop

Ry : 릴레이Ry: Relay

본 발명은 역상검출회로에 관한 것으로 특히 디지탈식 위상분리회로를 사용하는 역상검출회로에 관한 것이다.The present invention relates to a reverse phase detection circuit, and more particularly to a reverse phase detection circuit using a digital phase separation circuit.

삼상전력회로의 역상의 돌발사태를 최단시간안에 검출하여 사고를 미연에 방지해주는 것은 지극히 중대한 일이다.It is extremely important to detect the reverse phase of a three-phase power circuit in the shortest time and prevent accidents in advance.

따라서 본 발명은 기존의 미분, 적분 역상검출회로의 단점인 노이스인가 또는 순간 정진시 오동작 할 수 있는 단점을 제거하기 위하여 오동작을 최소화한 것을 제공하고자 하는것이 본 발명의 목적이다.Accordingly, an object of the present invention is to provide a minimized malfunction in order to eliminate a disadvantage that may be a malfunction in the case of noise application or instantaneous deterioration of a conventional derivative, integrated reverse phase detection circuit.

이하 본 발명을 실시예의 도면에 따라 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

즉 제 1 도는 본 발명의 실시예를 보여주는 회로도로 삼상전원연결단자(R.S.T)에는 각 상의 전압을 감압하고 여과하는 필터회로(M1, M2및 M3)를 통해 위상분리를 위해 NAND게이트(R1, R2및 R3)으로 되는 RS플립플롭회로에 입력되며 RS플립플롭 회로의 NAND 게이트(G1)의 출력(U)은 NAND게이트(G4)의 일측 입력단(X)에 그리고 RS플립플롭회로의 NAND게이트(G2)출력(V)은 다이오드(D)를 통해 상기한 NAND게이트(G4)의 타측 입력단(Y)에 연결됨과 동시에 콘덴서(C1)를 통해 접지되며, 또 RS플립플롭회로의 NAND게이트(G3)의 출력(W)은 인버터와 저항(R1)을 통해 에미터접지된 트랜지스터(Q1)의 베이스에 연결되고 콜렉터는 NAND게이트(G4)의 타측 입력단(Y)에 연결되어 있다.1 is a circuit diagram illustrating an embodiment of the present invention, a three-phase power connection terminal RST includes a NAND gate for phase separation through filter circuits M 1 , M 2, and M 3 for reducing and filtering the voltage of each phase. R 1 , R 2 and R 3 ) are input to the RS flip-flop circuit and the output (U) of the NAND gate (G 1 ) of the RS flip-flop circuit is connected to one input terminal (X) of the NAND gate (G 4 ) and RS The NAND gate (G 2 ) output (V) of the flip-flop circuit is connected to the other input terminal (Y) of the NAND gate (G 4 ) through the diode (D) and grounded through the capacitor (C 1 ), and The output W of the NAND gate G 3 of the RS flip-flop circuit is connected to the base of the emitter grounded transistor Q 1 through an inverter and a resistor R 1 , and the collector is the other side of the NAND gate G 4 . It is connected to the input terminal (Y).

또 상기한 NAND게이트 (G4)의 출력은 저항(R2)과 콘덴서(C4)로 되는 미분회로와 인버터의 출력(Z)이 저항(R3)을 통해 에미터 접지된 트랜지스터(Q2)의 베이스에 연결되어 있다.In addition, the output of the NAND gate (G 4 ) is a differential circuit consisting of a resistor (R 2 ) and a capacitor (C 4 ) and the output (Q) of the inverter is an emitter grounded transistor (Q 2 ) through the resistor (R 3 ) Is connected to the base.

따라서 상기 트랜지스터(Q2)의 콜렉터와 전원(Vcc)사이에는 릴레이(Mc)가 연결되어 도시하지 않은 전기적 접점을 제어하도록 됨을 공지와 같은 것이므로 설명의 간소화를 위하여 이에 대한 설명은 생략한다.Therefore, since the relay Mc is connected between the collector of the transistor Q 2 and the power supply Vcc to control an electrical contact (not shown), a description thereof will be omitted for simplicity.

도면중 미설명 부호 M4는 정전압 회로로 상기한 각 회로의 동작전원을 공급 하도록 된 것이며, 단자(P1, P2)는 정전시를 위하여 축전지 또는 전지 연결단자를 의미한다.In the figure, reference numeral M 4 denotes a constant voltage circuit to supply the operating power of each circuit described above, and terminals P 1 and P 2 refer to storage batteries or battery connection terminals for power failure.

상기와같은 본 발명의 실시예에 있어서 삼상연결단자(R.S.T)에 삼상의 교류전압이 인가되면, 각 단자(R.S.T)에는 제 2 도의 R.S.T와 같은 파형의 전압이 가해지고 이와같은 각 신호는 각 필터회로(M1, M2, M3)를 통해 NAND게이트(G1, G2, G3)로 되는 RS플립플롭 회로의 출력측(U, V, W)는 제 2 도의 U, V, W와 같은 파형과 같이 각 신호의 중복된 부분이 제거되고 NAND게이트(G4)와 트랜지스터(Q1)에 의해 위상의 정상여부를 항상 감시하게 되는바, 이때 NAND게이트(G2)의 출력(V)이 다이오드(D)를 통해 콘덴서(G)를 충진하는것과 NAND게이트(G3)의 출략(W)이 트랜지스터(Q1)에 인가되어 콘덴서(C1)를 방전회로에 의해 NAND게이트(G4)에 전달되는 신호회로의 로직회로의 신호가 상기 NAND게이트(G4)의 입력단(X, Y)에 인가될때 동시에 "1"이 되어 그 출력(Z)이 "1"일때 적어도 0.016sec이내에 릴레이(MC)코일을 가동시켜 공지와 같이 릴레이접점을 동작시켜 사고를 미연에 방지하게 되는 것이다.When the three-phase AC voltage is applied to the three-phase connection terminal (RST) in the embodiment of the present invention as described above, each terminal (RST) is applied a voltage of the waveform, such as RST of FIG. The output side (U, V, W) of the RS flip-flop circuit, which is connected to the NAND gates G 1 , G 2 , G 3 through the circuits M 1 , M 2 , M 3 , is different from U, V, W in FIG. Like the same waveform, the overlapped portion of each signal is removed and the phase is always monitored by the NAND gate G 4 and the transistor Q 1. In this case, the output V of the NAND gate G 2 is monitored. The capacitor (G) is charged through this diode (D) and the approach (W) of the NAND gate (G 3 ) is applied to the transistor (Q 1 ) so that the capacitor (C 1 ) is discharged by the discharge circuit to the NAND gate (G 4). ) is a logic circuit of a signal of the signal circuit when applied at the same time "1" at the input (X, Y) of said NAND gate (G 4) is passed to the output (Z) is "1" when at least 0.016sec By movable within the relay (MC) coil operates the relay contacts, as will be known to prevent accidents.

Claims (1)

NAND게이트(G1, G2, G3)로 구성되는 RS플립플롭회로에 삼상신호를 인가하는 필터(M1, M2, M3)회로와 NAND게이트(G12)의 출력(V)이 다이오드(D)와 콘덴서(C1)를 충전하도록 되고 NAND게이트(G3)의 출력(W)이 트랜지스터(Q1)에 인가되어 콘덴서(C1)를 방지시켜 NAND게이트(G4)신호(Z)로 로직회로를 구성하여서 되는 것을 특징으로 하는 역삼검출회로.A filter (M 1 , M 2 , M 3 ) circuit for applying a three-phase signal to an RS flip-flop circuit composed of NAND gates (G 1 , G 2 , G 3 ) and an output (V) of the NAND gate (G 1 2 ) The diode D and the capacitor C 1 are charged, and the output W of the NAND gate G 3 is applied to the transistor Q 1 to prevent the capacitor C 1 , thereby preventing the NAND gate G 4 signal ( Z) a reverse circuit detection circuit comprising a logic circuit.
KR1019900006812A 1990-05-14 1990-05-14 Emergency protective circuit KR930002747B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900006812A KR930002747B1 (en) 1990-05-14 1990-05-14 Emergency protective circuit

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Application Number Priority Date Filing Date Title
KR1019900006812A KR930002747B1 (en) 1990-05-14 1990-05-14 Emergency protective circuit

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KR910021029A KR910021029A (en) 1991-12-20
KR930002747B1 true KR930002747B1 (en) 1993-04-09

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KR1019900006812A KR930002747B1 (en) 1990-05-14 1990-05-14 Emergency protective circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324131B1 (en) * 1999-07-26 2002-02-20 장덕인 Three phase compensator

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