KR930002060B1 - Stack cell manufacturing method of t-type gate - Google Patents

Abstract

The method comprises (a) forming field oxide on the substrate, (b) depositing buffer oxide and poly into which N+ ions are implanted, (c) etching it using N+ S/D region as a mask, (d) depositing poly into which ions are not implanted and etching it vertically to form side walls, (e) depositing gate oxide, (f) depositing gate poly between N+ S/D regions, on which side walls are formed, to form T-type gate, (f) forming oxide for cap gate, (g) forming contact region with depression layer on N+ S/D region, (h) forming storage node poly, dielectric layer and plate poly thereon, (i) depositing oxide and doped on the plate poly and flowing, (j) forming bit line on N+ S/D region and depositing metal.

Description

Stack cell manufacturing method of T-type gate

1 is a conventional cross-sectional view of the process.

2 is a schematic view of the present invention.

3 is a cross-sectional view of the process of the present invention.

* Explanation of symbols for main parts of the drawings

1: field oxide film 2: buffer oxide film

3: Poly doped with N ⁺ S / D ions 4: Polyurethane

5: gate oxide film 6: gate poly

7: HTO 8: Storage Node Poly

9: dielectric 10: plate poly

11: BPSG 12: Metal

The present invention relates to a method for manufacturing a stacked cell of a T-type gate. In particular, the gate is formed in a T-type to increase the capacity of a capacitor by giving a lot of topology.

A detailed description of the conventional process is given below with reference to FIGS. 1A to 1E.

First, as shown in (A), a gate poly 6 is formed, and then N ⁺ source / drain ions (hereinafter referred to as S / D) ions are implanted. Subsequently, as shown in (B), a buried layer contact region is formed and the storage node poly 8 is deposited, then defined and etched.

Subsequently, in order to form an oxide film / nitride film / oxide film (hereinafter referred to as ONO), which is the dielectric 9 of the capacitor, as shown in (C), an oxide film is formed, the plate poly 10 is deposited, and then limited and etched.

Then, as shown in (D), the BPSG 11, which is a doped oxide film, is deposited and flowed.

Finally, as shown in (E), the N ⁺ S / D contact region is formed, and then the metal 12 is deposited to form a bit line.

The stack cell manufactured as described above has a disadvantage in that the gate capacity is formed in a “-” shape so that the topography is small and the area of the capacitor is small.

In addition, since the N ⁺ S / D region is present on the silicon substrate, the junction capacitance increases, which affects the speed of the memory and reduces the junction leakage current.

The present invention is to eliminate the above disadvantages and the process thereof will be described below with reference to FIGS. 2 and 3 (A) to (I). First, as shown in (A), a field oxide film 1 is formed on a silicon substrate, and a buffer oxide film 2 and a doped poly 3 doped with N ⁺ S / D ions are sequentially deposited.

Next, as shown in (B), the doped poly 3 and the buffer oxide film 2 are etched using N ⁺ S / D as a mask. Next, as shown in (C) (D), the undoped sidewall poly 4 is deposited and vertically etched to form sidewalls, and then the gate oxide film 5 is formed.

Subsequently, as shown in (E) (F), the gate poly (6) is deposited and etched to limit it. Then, the HTO (7) is deposited using the buried layer contact portion as a mask. Etch. In this case, the HTO 7 may be used as a low temperature oxide (LTO) instead.

Then, as shown in (G), the storage node poly 8 is deposited and then etched by defining it. Then, the dielectric 9 of the capacitor is formed by forming an ONO, and then the plate poly 10 is deposited and limited by the etching.

Finally, the HTO 7a and the BPSG 11 are sequentially deposited and flowed as in (H) (I), and then an N ⁺ S / D contact region is formed and the metal 12 is deposited thereon to complete the process. . The stack cell according to the present invention manufactured as described above has the following effects.

First, as shown in FIG. 2, the gate is formed in a “T” shape, thereby increasing the topology, thereby increasing the area of the capacitor.

Second, since a portion of N ⁺ S / D is present on the buffer oxide film 2, the junction leakage current and junction capacitance are reduced, thereby reducing the speed reduction in the memory.

Third, since the bonding area exposed to the silicon substrate is small, it is also improved in terms of soft error.

Fourth, the contact area is increased when the storage node poly 8 or the metal 12 is connected to N ⁺ S / D, it is possible to reduce the contact resistance.

Fifth, since a portion of N ⁺ S / D is located above the silicon substrate, the aspect ratio may be improved when the metal 12 is deposited.

Sixth, the thicker the doped poly (3) doped with N ⁺ S / D ions can increase the capacity of the cell capacitor, wherein the aspect ratio of the buried layer and the metal contact region is the same regardless.

Claims (1)

Forming a field oxide film on the substrate, depositing a buffer oxide film and polyimplanted N ⁺ S / D ions in turn, and then etching the N ⁺ S / D region as a mask; Vertical etching to form a sidewall and depositing a gate oxide film, depositing a gate poly between the N ⁺ S / D regions where the sidewall is formed to form a T-type gate, and forming a high temperature oxide film for a capgate thereon; Forming a buried layer contact region in the N ⁺ S / D region, and forming a storage node poly, a dielectric layer, and a plate poly on the plate poly; phase, T-shaped gate, characterized by made of an step of forming a bit line contact region on that capacitor is not formed N ⁺ S / D regions, and depositing a metal Cell stack manufacturing method.

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