KR930001840Y1 - Lcd with tft - Google Patents
Lcd with tft Download PDFInfo
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- KR930001840Y1 KR930001840Y1 KR2019890021031U KR890021031U KR930001840Y1 KR 930001840 Y1 KR930001840 Y1 KR 930001840Y1 KR 2019890021031 U KR2019890021031 U KR 2019890021031U KR 890021031 U KR890021031 U KR 890021031U KR 930001840 Y1 KR930001840 Y1 KR 930001840Y1
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- 239000010409 thin film Substances 0.000 claims description 32
- 239000010408 film Substances 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133302—Rigid substrates, e.g. inorganic substrates
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Abstract
내용 없음.No content.
Description
제1도는 종래의 용장성 박막 트랜지스터를 채용한 액정표시소자의 평면도.1 is a plan view of a liquid crystal display device employing a conventional redundancy thin film transistor.
제2도는 제1도의 하나의 화소부분을 구동시키기 위한 박막 트랜지스터의 단면도.2 is a cross-sectional view of a thin film transistor for driving one pixel portion of FIG.
제3도는 본 고안의 용장성 박막 트랜지스터를 채용한 액정표시소자의 평면도.3 is a plan view of a liquid crystal display device employing the redundant thin film transistor of the present invention.
제4도는 제3도의 하나의 화소수분을 구동시키기 위한 박막 트랜지스터의 단면도.4 is a cross-sectional view of a thin film transistor for driving one pixel moisture of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 12 : 유리기판 20, 21, 22 : 게이트 전극11, 12: glass substrate 20, 21, 22: gate electrode
31, 32 : 절연막 40, 41, 42 : 소오스전극31, 32 insulating film 40, 41, 42 source electrode
51, 52 : 드레인 전극 61, 62 : ITO전극51, 52: drain electrode 61, 62: ITO electrode
70, 71, 72 : 블랙 매트릭스 9 : 화소70, 71, 72: Black Matrix 9: Pixel
81 : 소오스라인 82 : 게이트 라인81: source line 82: gate line
본 고안은 용장성 박막 트랜지스터를 채용한 액정표시 소자에 관한 것으로서, 특히 하나의 화소를 양분하고 양분된 화소 사이에 게이트 라인을 형성하여 하나의 박막 트랜지스터로 하나의 화소를 구동시키는 액정표시소자에 관한 것이다.The present invention relates to a liquid crystal display device employing a redundancy thin film transistor, and more particularly, to a liquid crystal display device that divides one pixel and forms a gate line between the divided pixels to drive one pixel with one thin film transistor. will be.
제1도는 종래의 용장성 박막 트랜지스터를 채용한 액정표시소자의 평면도를 나타낸 것으로서, 부호 9는 하나의 화소를 나타내는 것이다.FIG. 1 is a plan view of a liquid crystal display device employing a conventional redundancy thin film transistor, and reference numeral 9 denotes one pixel.
화소(9)는 두 부분으로 나뉘어져서 이를 구동시키기 위하여 제1도에 도시한 바와 같은 두개의 용장성 박막 트랜지스터(91), (92)가 사용되고 있으며, 두 부분으로 나뉘어진 한 화소의 각 부분을 구동시키는 용장성 박막 트랜지스터(91), (92)에 있어서 각 소오스전극은 소오스라인(81)을 통하여 공통 소오스전극(40)에 연결되어 있으며, 각 게이트전극은 게이트라인(82)을 통하여 공통 게이트전극(20)에 연결되어 있다.The pixel 9 is divided into two parts, and two redundant thin film transistors 91 and 92 are used as shown in FIG. 1 to drive them, and each part of one pixel divided into two parts is used. In the redundant thin film transistors 91 and 92 to be driven, each source electrode is connected to a common source electrode 40 through a source line 81, and each gate electrode is connected to a common gate through a gate line 82. It is connected to the electrode 20.
이때, 화소와 화소 사이에는 도면에서 보는 바와 같이 게이트라인(82)과 소오스라인(1)이 병렬로 위치하여 2회 이상교차하게 된다.In this case, as shown in the drawing, the gate line 82 and the source line 1 are disposed in parallel and cross each other two or more times.
제2도는 제1도의 한 화소(9)의 두부분중 하나의 부분을 구동시키기 위한 용장성 박막트랜지스터의 단면도를 나타낸 것으로서, 한 화소가 2부분으로 나뉘어져 있어서 각 부분을 구동시키는 데 하나의 박막 트랜지스터가 필요하기 때문에 종래의 액정표시소자의 경우에는 한 화소를 구동시키기 위해서는 2개의 박막 트랜지스터(91, 92)가 사용된다.FIG. 2 is a cross-sectional view of a redundant thin film transistor for driving one of two parts of one pixel 9 of FIG. 1, wherein one pixel is divided into two parts so that one thin film transistor is used to drive each part. In the conventional liquid crystal display device, two thin film transistors 91 and 92 are used to drive one pixel.
제1도의 한 화소(9)중 화소(91) 부분을 구동시키기 위한 용장성 박막 트랜지스터는 하부 유리기판(11) 상에 게이트전극(21)이 형성되어 있으며, 절연막(31, 32)에 의해 게이트전극(21)과 절연되어 소오스전극(41)과 드레인전극(51)이 게이트전극(21)의 상부에 형성되어 있으며, 투명도전막(61)이 절연막(32)상에 형성되어 드레인전극(51)에 접촉되게 된다.In the redundant thin film transistor for driving the pixel 91 portion of one pixel 9 of FIG. 1, a gate electrode 21 is formed on a lower glass substrate 11, and gates are formed by insulating layers 31 and 32. The source electrode 41 and the drain electrode 51 are insulated from the electrode 21 and formed on the gate electrode 21, and the transparent conductive film 61 is formed on the insulating film 32 to form the drain electrode 51. Will be in contact with.
또한, 상부 유리기판(12) 상에는 상기 소오스전극(41) 드레인전극(51) 및 게이트전극(21)에 대응하여 빛을 차단하기 위한 블랙 매트릭스(71)가 형성되어 있다.In addition, a black matrix 71 is formed on the upper glass substrate 12 to block light corresponding to the source electrode 41, the drain electrode 51, and the gate electrode 21.
다른 화소부분(92)을 구동시키기 위한 용장석 박막 트랜지스터도 상기와 동일한 구조로 되어 있다.The agolite thin film transistor for driving the other pixel portion 92 has the same structure as above.
즉 제1도의 한 화소(9)중 화소(92)부분을 구동시키기 위한 용장성 박막 트랜지스터는 하부 유리기판(11)상에 게이트전극(22)이 형성되어 있으며, 절연막(31, 32)에 의해 게이트전극(22)과 절연되어 소오스전극(2)과 드레인전극(52)이 게이트전극(22)이 상부에 형성되어 있으며, 투명도전막(2)이 절연막(32) 상에 형성되어 드레인전극(52)에 접촉되게 된다.That is, in the redundant thin film transistor for driving the pixel 92 portion of one pixel 9 of FIG. 1, the gate electrode 22 is formed on the lower glass substrate 11, and the insulating films 31 and 32 are used to form the thin film transistor. Insulated from the gate electrode 22, the source electrode 2 and the drain electrode 52 are formed on the gate electrode 22, and the transparent conductive film 2 is formed on the insulating film 32 to form the drain electrode 52. )
또한, 상부 유리기판(12)상에는 상기 소오스전극(42)드레인전극(52) 및 게이트전극(22)에 대응하여 빛을 차단하기 위하여 블랙 매트릭스(72)가 형성되어 있다.In addition, a black matrix 72 is formed on the upper glass substrate 12 so as to block light corresponding to the source electrode 42, the drain electrode 52, and the gate electrode 22.
상기한 종래의 용장성 박막 트랜지스터를 채용한 액정표시소자는 하나의 화소를 구동시키기 위하여 2개의 박막 트랜지스터가 사용되고 있는데, 이러한 박막 트랜지스터를 용장성이기 때문에 게이트전극을 공통 게이트전극에 연결시키기 위한 게이트라인과 소오스전극을 공통 소오스전극에 연결시켜 주기 위한 소오스라인이 추가적으로 사용되어야 한다. 이로 인하여 화소간의 간격이 넓어지게 되고, 화소간격이 넓어짐에 따라 전체적인 화소의 크기는 작아지게 되는 문제점이 있다.In the liquid crystal display device employing the conventional redundancy thin film transistor, two thin film transistors are used to drive one pixel. Since the thin film transistor is redundant, a gate line for connecting the gate electrode to the common gate electrode and A source line for connecting the source electrode to the common source electrode should be additionally used. As a result, the spacing between pixels becomes wider, and as the pixel spacing widens, the size of the entire pixel becomes smaller.
또한, 이러한 용장성 박막 트랜지스터는 화소와 화소사이에 게이트라인과 소오스라인이 병렬로 위치해 있어 두 라인이 2회 이상 교차함으로써 두 라인간의 단락 및 오픈이 발생하는 확률이 높아져 제조 수율이 저하되는 문제점이 있었다.In addition, since the gate line and the source line are disposed in parallel between the pixel and the pixel, the redundant thin film transistor has a problem in that the yield of the short circuit and open between the two lines increases and thus the manufacturing yield is reduced. there was.
본 고안은 상기한 종래 기술의 문제점을 해결하기 위한 것으로서, 하나의 용장성 박막 트랜지스터로 하나의 화소를 구동시켜 화소의 면적을 증대시킬 수 있는 용장성 박막 트랜지스터를 채용한 액정표시소자를 제공하는 데 있다.The present invention is to solve the above-mentioned problems of the prior art, to provide a liquid crystal display device employing a redundant thin film transistor that can increase the area of the pixel by driving one pixel with one redundant thin film transistor. have.
상기 목적을 달성하기 위한 본 고안은, 하나의 화소를 두 부분으로 양분하고 양분된 화소간에 게이트라인을 통과시켜 박막 트랜지스터를 게이트라인의 근거리에 위치시키고, 화소와 화소사이에 게이트라인과 소오스 라인이 병렬로 1회만 교차하도록 하는 것을 특징으로 한다.In order to achieve the above object, the present invention divides one pixel into two parts and passes the gate line between the divided pixels so that the thin film transistor is positioned near the gate line. It is characterized in that only one crossing in parallel.
본 고안에 있어서, 용장성 박막 트랜지스터는 하부 유리기판상에 게이트전극이 절연막에 의해 절연되어 이웃하게 형성되고, 상기 게이트 전극의 상부에는 절연막에 의해 절연되어 소오스 전극이 접촉되어 형성됨과 동시에 상기 소오스 전극을 사이에 두고 투명도전막과 접촉된 드레인 전극이 서로 대향되어 형성되어 있으며, 상부 유리기판 상에는 상기 소오스전극, 드레인전극 및 게이트 전극에 대응하여 블랙 매트릭스가 설치되어 있는 것을 특징으로 한다.In the present invention, a redundant thin film transistor is formed adjacent to a gate electrode insulated by an insulating film on a lower glass substrate, and is formed by contacting a source electrode by being insulated by an insulating film on an upper portion of the gate electrode. The drain electrodes which are in contact with each other with the transparent conductive film interposed therebetween are formed to face each other, and a black matrix is disposed on the upper glass substrate corresponding to the source electrode, the drain electrode, and the gate electrode.
이하 본 고안의 실시예를 첨부된 도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 고안의 액정표시소자의 평면도를 나타낸 것으로서, 부호 9는 하나의 화소를 나타내는 것이다.3 is a plan view of the liquid crystal display device of the present invention, and reference numeral 9 denotes one pixel.
하나의 화소는 두 부분(91, 92)으로 양분되어 제4도에 도시한 하나의 용장성 박막 트랜지스터에 의해 구동되고, 이 용장성 박막 트랜지스터에 있어서 양분된 화소부분(91, 92) 사이에 게이트라인(82)을 통과시켜 게이트라인을 박막 트랜지스터에 근거리에 위치시키고, 화소와 화소 사이에 게이트라인(82)과 소오스라인(81)이 병렬로 1회만 교차하도록 한다.One pixel is divided into two portions 91 and 92 and driven by one redundant thin film transistor shown in FIG. 4. In this redundant thin film transistor, a gate is divided between the divided pixel portions 91 and 92. A line 82 is passed through the line 82 so that the gate line is positioned near the thin film transistor, and the gate line 82 and the source line 81 intersect only once in parallel between the pixel and the pixel.
본 고안에 있어서, 용장성 박막 트랜지스터는 제4도에 도시한 바와 같이 하부 유리기판(11)상에 게이트전극(21, 22)이 절연막(31)에 의해 절연되어 이웃하게 형성되고, 상기 게이트전극(21, 22)의 상부에는 절연막(31, 32)에 의해 절연되어 소오스 전극(41, 42)이 접속되어 형성됨과 동시에 상기 소오스전극(41, 42)을 사이에 두고 드레인전극(51, 52)이 서로 대향되어 형성되어 있으며, 투명도전막(61, 62)이 상기 드레인전극(51, 52)과 접촉되어 형성되어 있다.In the present invention, in the redundant thin film transistor, as illustrated in FIG. 4, gate electrodes 21 and 22 are insulated from each other by an insulating layer 31 on the lower glass substrate 11, and the gate electrode is formed. The source electrodes 41 and 42 are connected to each other by being insulated by the insulating layers 31 and 32 on the upper portions 21 and 22, and the drain electrodes 51 and 52 with the source electrodes 41 and 42 interposed therebetween. They are formed to face each other, and the transparent conductive films 61 and 62 are formed in contact with the drain electrodes 51 and 52.
또한, 상부 유리기판(12)상에는 상기 유리기판(12)상에는 상기 소오스전극(41, 42), 드레인전극(51, 52) 및 게이트전극(21, 22)에 대응하여 빛을 차단하기 위하여 하나의 블랙 매트릭스(70)가 설치되어 있다.In addition, on the upper glass substrate 12, a light is blocked on the glass substrate 12 so as to block light in response to the source electrodes 41 and 42, the drain electrodes 51 and 52, and the gate electrodes 21 and 22. The black matrix 70 is provided.
상기 하나의 화소(9)는 종래와 마찬가지로 두 부분으로 양분되어 있으나, 이 양분된 화소부분(91)과 (92)사이에는 게이트라인(82)이 통과하므로 게이트라인(82)은 화소와 아주 근거리에 위치해 있게 된다. 그러므로, 게이트라인을 극소화시킬 수 있으며, 또한 게이트라인과 소오스라인의 교차횟수가 화소당 1회로 감소하게 된다.The single pixel 9 is divided into two parts as in the prior art, but since the gate line 82 passes between the divided pixel parts 91 and 92, the gate line 82 is very near to the pixel. It will be located at. Therefore, the gate line can be minimized, and the number of crossings between the gate line and the source line is reduced to one per pixel.
상기한 바와같은 본 고안에 의하면, 게이트라인의 확장을 극소화시키므로써 화소의 면적을 증대시켜 개구율을 증가시킬 수 있으며, 게이트라인 및 소오스 라인의 교차횟수를 줄이므로써 단락 및 오픈 등에 의한 불량율을 감소시킬 수 있어 생산수율을 향상시킬 수 있다.According to the present invention as described above, by minimizing the expansion of the gate line, the area of the pixel can be increased to increase the aperture ratio, and the defect rate due to short-circuit and open can be reduced by reducing the number of crossings of the gate line and the source line. Can improve the production yield.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890021031U KR930001840Y1 (en) | 1989-12-30 | 1989-12-30 | Lcd with tft |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890021031U KR930001840Y1 (en) | 1989-12-30 | 1989-12-30 | Lcd with tft |
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| Publication Number | Publication Date |
|---|---|
| KR910012325U KR910012325U (en) | 1991-07-30 |
| KR930001840Y1 true KR930001840Y1 (en) | 1993-04-15 |
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| KR2019890021031U KR930001840Y1 (en) | 1989-12-30 | 1989-12-30 | Lcd with tft |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020046242A (en) * | 2002-04-20 | 2002-06-20 | 승 훈 최 | A fish-hook use the fish-signal tools |
| KR20040009461A (en) * | 2002-07-23 | 2004-01-31 | 김용옥 | System for charging float wirelessly |
-
1989
- 1989-12-30 KR KR2019890021031U patent/KR930001840Y1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020046242A (en) * | 2002-04-20 | 2002-06-20 | 승 훈 최 | A fish-hook use the fish-signal tools |
| KR20040009461A (en) * | 2002-07-23 | 2004-01-31 | 김용옥 | System for charging float wirelessly |
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| Publication number | Publication date |
|---|---|
| KR910012325U (en) | 1991-07-30 |
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