KR930001680A - Video signal clamp circuit - Google Patents

Video signal clamp circuit Download PDF

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Publication number
KR930001680A
KR930001680A KR1019910009493A KR910009493A KR930001680A KR 930001680 A KR930001680 A KR 930001680A KR 1019910009493 A KR1019910009493 A KR 1019910009493A KR 910009493 A KR910009493 A KR 910009493A KR 930001680 A KR930001680 A KR 930001680A
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KR
South Korea
Prior art keywords
video signal
clamp circuit
difference
converter
value
Prior art date
Application number
KR1019910009493A
Other languages
Korean (ko)
Inventor
히데또시 오자끼
아끼라 고꾸라
Original Assignee
보조 다꾸로
니뽕 빅터 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 보조 다꾸로, 니뽕 빅터 가부시끼가이샤 filed Critical 보조 다꾸로
Priority to KR1019910009493A priority Critical patent/KR930001680A/en
Publication of KR930001680A publication Critical patent/KR930001680A/en

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Abstract

내용 없음No content

Description

비디오 신호 클램프 회로Video signal clamp circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따르는 비디오 신호 클램프 회로의 블럭 구성도.1 is a block diagram of a video signal clamp circuit according to the present invention.

제2도는 동 회로의의 실시예의 블럭 구성도.2 is a block diagram of an embodiment of the circuit.

제3도는 제3실시예의 블럭 구성도.3 is a block diagram of a third embodiment.

Claims (1)

아날로그 비디오 신호에 대해서 바이어스 전압에 의거해서 직류성분의 조절을 한 아나로그 비디오 신호를 출력하는 직류 레벨 시프트 회로와, 이 직류 레벨 시프트 회로에서 출력된 아나로그 비디오 신호를 디지탈 비디오신호로 변환하는 A/D 변환기를 구비한 비디오 신호 클램프 회로에 있어서, 상기한 바이어스 전압에 따른 전압출력을 발생하는 D/A 변환기를 구비하여, 상기한 디지탈 비디오 신호의 값과 클램프 레벨에 따른 값과의 차에 대응하는 차 대응값을 전귀환형 디지탈 필터를 거쳐서 상기한 D/A 변환기에 입력함과 함께, 상기한 전귀환형 디지탈 필터는 전회입력된 차대응값에 금회에 입력된 차대응값을 가산한 값을 상기한 D/A 변환기에 출력하도록 구성한 것을 특징으로 하는 비디오 신호 클램프 회로.A DC level shift circuit for outputting an analog video signal whose DC component is adjusted based on a bias voltage for an analog video signal, and A / for converting an analog video signal output from the DC level shift circuit into a digital video signal. A video signal clamp circuit having a D converter, the video signal clamp circuit comprising a D / A converter for generating a voltage output according to the bias voltage, wherein the video signal clamp circuit corresponds to a difference between the value of the digital video signal and the value according to the clamp level. The difference-corresponding value is inputted to the D / A converter via a pre-feedback digital filter, and the pre-feedback digital filter adds the difference obtained by adding the difference value input this time to the difference value previously input. A video signal clamp circuit, configured to output to a D / A converter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009493A 1991-06-10 1991-06-10 Video signal clamp circuit KR930001680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009493A KR930001680A (en) 1991-06-10 1991-06-10 Video signal clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009493A KR930001680A (en) 1991-06-10 1991-06-10 Video signal clamp circuit

Publications (1)

Publication Number Publication Date
KR930001680A true KR930001680A (en) 1993-01-16

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ID=67440723

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009493A KR930001680A (en) 1991-06-10 1991-06-10 Video signal clamp circuit

Country Status (1)

Country Link
KR (1) KR930001680A (en)

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E601 Decision to refuse application