KR930001416B1 - Method of generating cell plate voltage and circuit thereof - Google Patents

Method of generating cell plate voltage and circuit thereof Download PDF

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KR930001416B1
KR930001416B1 KR1019900010614A KR900010614A KR930001416B1 KR 930001416 B1 KR930001416 B1 KR 930001416B1 KR 1019900010614 A KR1019900010614 A KR 1019900010614A KR 900010614 A KR900010614 A KR 900010614A KR 930001416 B1 KR930001416 B1 KR 930001416B1
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South Korea
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voltage
vcp
cell plate
circuit
vbb
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KR1019900010614A
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Korean (ko)
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KR920003510A (en
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김주한
심재광
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금성일렉트론 주식회사
문정환
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Priority to KR1019900010614A priority Critical patent/KR930001416B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The circuit prevents latch up of D-RAM when power is turned on by delaying substrate and cell plate voltage generation starting time. The circuit includes a VBB signal generating circuit for generating VBB signal when power is turned on, a substrate voltage detecting circuit (16) for detecting VBB signal, a low impedance driver (17) for setting VCP voltage when VBB signal level decreases to VBBT level and a highimpedance VCP maintainer (18) for maintaining VCP voltage level when VBB signal level increases to VCC/2. The cell plate voltage is set by the low impedance driver when power is turned on and is maintained by the high impedance VCP maintainer driver after the cell plate voltage is set.

Description

셀 플레이트 전압 발생방법 및 회로Cell plate voltage generation method and circuit

제1도와 제2도는 종래의 회로도.1 and 2 are conventional circuit diagrams.

제3도는 제1도에서의 파형도.3 is a waveform diagram in FIG.

제4도는 본 발명의 회로도.4 is a circuit diagram of the present invention.

제5도는 제4도에서의 파형도.5 is a waveform diagram in FIG.

제6도는 본 발명의 실시예 회로도.6 is an embodiment circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 비트선 11 : 워드선10: bit line 11: word line

12 : 셀 플레이트 전압 발생회로 13 : 서브스트레이트전압발생회로12: cell plate voltage generating circuit 13: substrate voltage generating circuit

14 : 기판 바이어스 제어회로부 15 : 파워 온 리셋14 substrate bias control circuit 15 power on reset

16 : 기판 전압 감지 회로부 17 : 로우 임피던스 드라이버16 substrate voltage sensing circuit 17 low impedance driver

18 : 하이 임파던스 VCP 메인테이너18: High Impedance VCP Maintainer

본 발명은 반도체 메모리, 특히 디램에 관한 것으로 상보형 모스(CMOS) 공정기술을 이용한 디램에 있어서 파워업(Power-Up)시의 안정적 동작에 적당하도록 한 회로 설계 기술중 기판과 캐패시티브 커플링되어 있는 셀플레이트 전압 발생회로에 의한 기판의 포워드 바이어싱(Forward Biasing) 가능성을 배제한 셀플레이트 전압 발생방법 및 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory, in particular to a DRAM, wherein a substrate and a capacitive coupling in a circuit design technique adapted to a stable operation during power-up in a DRAM using a complementary MOS process technology. The present invention relates to a cell plate voltage generation method and circuit that eliminates the possibility of forward biasing of a substrate by a cell plate voltage generation circuit.

제1도는 종래의기술구성으로서 파워업시 플로팅(floating)되어 있는 기판과 셀플레이트 전압 발생회로이다.FIG. 1 shows a substrate and cell plate voltage generation circuit floating in power up as a conventional technical configuration.

제2도는 제1도에서의 파형도이다.2 is a waveform diagram of FIG. 1.

제1도에서 파워업시 P형 기판(P-Sub)은 플로팅 되어 있는 상태에서 기판 전압 발생회로(13)가 동작하면서 서브에서 전하 펌핑에 의해 그 바이어스 상태가 정해지게 되어 있다.In FIG. 1, the bias state is determined by charge pumping in the sub while the P-sub substrate P-Sub is in a floating state while the substrate voltage generation circuit 13 operates.

이때 기판 전압 발생회로와 함께 셀플레이트 전압(이후 VCP) 또한 상승하게 된다. 이러한 상황하에서 기판의 상태를 보면 캐패시터 CJ 및 CS를 통한 커플링에 의한 전압 상승과 VBB발생회로(13)로부터 펌핑 되어온 음전하(Electron)에 의한 전압 강하가 동시에 일어난다. 제1도에서 R Sub는 기판의 저항이고 RW는 VCP 연결에 들어간 저항이다.At this time, the cell plate voltage (hereinafter referred to as VCP) also increases along with the substrate voltage generation circuit. In this situation, when the substrate is viewed, the voltage rise due to the coupling through the capacitors CJ and CS and the voltage drop due to the negative charge pumped from the VBB generation circuit 13 occur simultaneously. In Figure 1, R Sub is the resistance of the substrate and RW is the resistance entered into the VCP connection.

VBB발생회로에서 먼쪽에 있는 셀들의 경우 R Sub가 커질 것이다. 즉 VCP의 상승에 의한 커플링이 VBB에 의한 전압 강하보다 훨씬 큰쪽에서는 P형 기판이 포워드 바이어스 될 가능성이 있다. 또한 제2도는 파워 업 도중에는 기판이 접지됨으로 해서 안정될 수 있으나 파워가 일정한 전압 상태에 이른후에는 다시 기판을 플로팅한 상태에서 VBB발생회로에 의해 다시 바이어스를 만들기 때문에 제1도에서와 같은 문제점을 안고 있다.For the cells farthest from the VBB generation circuit, R Sub will be large. In other words, if the coupling due to the rise of VCP is much larger than the voltage drop due to VBB, the P-type substrate may be forward biased. In addition, FIG. 2 may be stabilized by grounding the substrate during power-up, but after the power reaches a constant voltage state, the same problem as in FIG. Holding it.

미설명 부호 10은 비트선, 11은 워드선, 12는 셀플레이트 전압 발생회로, 14는 기판 바이어스 제어회로부, 15는 파워 온 리셋이다. 이와같이 종래의 기술에서는 파워업시 기판 전압 발생과 셀플레이트 전압 발생간에 아무런 시간적 차이 또는 제어방식이 없기 때문에 기판의 국부적 포워드 바이어싱 가능성이 있고, 포워드 바이어싱이 된 P형 기판에 주위의 n+ 정션으로부터 인젝션이 일어나고 곧바로 래치업에 빠지게 된다.Reference numeral 10 denotes a bit line, 11 a word line, 12 a cell plate voltage generation circuit, 14 a substrate bias control circuit section, and 15 a power on reset. As described above, since there is no time difference or control method between the generation of the substrate voltage and the generation of the cell plate voltage during power-up, there is a possibility of local forward biasing of the substrate, and injection from the surrounding n + junction to the P-type substrate which has been forward biased. This happens and you're in latch-up right away.

이렇게해서 파워업 도중에 생긴 래치업은 파워가 다시 오프되기전까지는 회복되지 않아 메모리동작의 실패를 가져오고 래치-업시의 과다한 전류에 의한 소자의 영구 파괴를 가져올 위험이 있다. 제4는 본 발명의 회로도 이고, 제5도는 제4도에서의 파형도인데, VBB발생회로부(13)가 파워업 후 동작을 먼저 시작하여 제5도와 같이 VBB신호가 VBBT까지 내려가면 기판 전압 감지 회로부(16)가 로우 임피던스 드라이버(17)를 동작시켜서 VCP전압이 1/2Vcc가 되게 한다. 로우임피던스 드라이버(17)는 VCP가 1/2Vcc까지 올라가면 동작을 중단하고 이후에는 하이임피던스 VCP 메인테이너(18)는 VCP레벨을 유지한다.In this way, the latch-up generated during power-up does not recover until the power is turned off again, resulting in the failure of the memory operation and the risk of permanent destruction of the device by excessive current during latch-up. FIG. 4 is a circuit diagram of the present invention, and FIG. 5 is a waveform diagram of FIG. 4, wherein the VBB generation circuit unit 13 starts the operation after power-up first and detects the substrate voltage when the VBB signal drops to VBBT as shown in FIG. The circuit section 16 operates the low impedance driver 17 so that the VCP voltage is 1 / 2Vcc. The low impedance driver 17 stops operation when the VCP rises to 1/2 Vcc, after which the high impedance VCP maintainer 18 maintains the VCP level.

제6도는 본 발명의 실시예 회로도로서 파워업 후에 노드 34가 캐패시터(19)에 의해 하이가 되고, 노드34에 의해 트랜지스터(24)를 도통시켜서 VCP가 접지가 되었다가 VBB발생회로(13)가 동작을 시작하여 VBB의 전압이 -2VT(VT : 문턱전압)가 되면 트랜지스터(21, 22)가 도통되어 노드 34가 로우가 되어 트랜지스터(24)는 불통되고 트랜지스터(28)가 도통된다.FIG. 6 is a circuit diagram of an embodiment of the present invention. After powering up, node 34 becomes high by capacitor 19, and transistor 34 is energized by node 34, and VCP is grounded. When the operation starts and the voltage of VBB becomes -2VT (VT: threshold voltage), the transistors 21 and 22 are turned on, and the node 34 is turned low so that the transistor 24 is turned off and the transistor 28 is turned on.

이때 노드 35가 하이 임피던스 VCP 메인테이너에 의해 하이가 되어 있으므로 트랜지스터(28)가 도통되면서 VCP의 전압이 올라게 된다. VCP가 Vcc/2까지 올라가면 트랜지스터(26)가 도통되어 노드 35를 로우로 낮추어 트랜지스터(25)를 불통시킴으로서 로우 임피던스 드라이버의 동작은 정지되고 VCP 전압은 하이 임피던스 VCP 메인 테이너에 의해서만 유지된다.At this time, since the node 35 is made high by the high impedance VCP maintainer, the voltage of the VCP rises as the transistor 28 becomes conductive. When VCP rises to Vcc / 2, transistor 26 is turned on, bringing node 35 low to disable transistor 25 so that low impedance driver operation is stopped and the VCP voltage is maintained only by the high impedance VCP maintainer.

하이임피던스 VCP 메인테이너는 파워업후 저항(32, 33)과 트랜지스터(27, 29)에 의해 노드 36과 노드 37이 바이어싱되어 트린지스터(28, 30)를 구동하여 VCP의 전압을 일정하게 유지하도록 한다.The high-impedance VCP maintainer allows nodes 36 and 37 to be biased by resistors 32, 33 and transistors 27, 29 after power-up to drive transistors 28, 30 to maintain a constant voltage at VCP. .

따라서 본 발명의 셀플레이트 전압 발생방법 및 회로는 파워업시 기판 전압 발생과 셀플레이트 전압 발생 시점의 시간을 지연시켜서 기판의 국부적 순방향 바이어스 가능성을 제거함으로서 파워업시에 발생할 수 있는 래치업을 방지한다.Accordingly, the cell plate voltage generation method and circuit of the present invention delays the time between the generation of the substrate voltage at the time of power up and the time of the generation of the cell plate voltage, thereby eliminating the possibility of local forward bias of the substrate, thereby preventing latch-up that may occur at power-up.

Claims (2)

파워업시 VBB전압을 감지하여 로우 임피던스 드라이버로 셀플레이트 전압을 셋업시키고, 셀플레이트 전압이 셋업된 후에는 하이임피던스 드라이버에 의해 셀플레이트 전압을 유지하는 셀플레이트 전압 발생방법.A method of generating a cell plate voltage by sensing a VBB voltage at power up to set up a cell plate voltage with a low impedance driver and maintaining the cell plate voltage by a high impedance driver after the cell plate voltage is set up. 파워업 후 VBB신호를 발생하는 VBB발생회로와, 상기 VBB발생회로부에서 발생된 VBB신호를 감지하는 기판 전압 감지 회로부와, VBB신호가 VBBT까지 내러가면 상기 기판 전압 감지회로부에 의해 선택 동작하여 VCP전압을 셋업시키는 로우 임피던스 드라이버와 VBB신호가 VCC/2까지 올라가면 기판 전압 감지회로부에 의해 선택동작하여 VCP전압을 유지시키는 VCP 메인테이너를 포함하여 구성된 것을 특징으로 하는 셀플레이트 전압 발생회로.A VBB generation circuit for generating a VBB signal after power-up, a substrate voltage sensing circuit unit for sensing the VBB signal generated by the VBB generation circuit unit, and a VCP voltage selected by the substrate voltage sensing circuit unit when the VBB signal reaches VBBT And a VCP maintainer configured to maintain a VCP voltage by selectively operating by the substrate voltage sensing circuit unit when the VBB signal rises to VCC / 2.
KR1019900010614A 1990-07-13 1990-07-13 Method of generating cell plate voltage and circuit thereof KR930001416B1 (en)

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KR1019900010614A KR930001416B1 (en) 1990-07-13 1990-07-13 Method of generating cell plate voltage and circuit thereof

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KR930001416B1 true KR930001416B1 (en) 1993-02-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7680329B2 (en) 2005-08-22 2010-03-16 Kabushiki Kaisha Toshiba Character recognition apparatus and character recognition method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7680329B2 (en) 2005-08-22 2010-03-16 Kabushiki Kaisha Toshiba Character recognition apparatus and character recognition method

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