KR930001400Y1 - Interface unit for monitor - Google Patents

Abstract

No content.

Description

Monitor interface circuit

1 is an interface circuit of a conventional monitor

2 is a waveform diagram of a main part of an interface circuit of a conventional monitor.

3 is a block diagram of an interface circuit of a monitor according to the present invention.

4 is a conversion circuit diagram configured in the interface circuit of the monitor according to the present invention.

* Explanation of symbols for main parts of the drawings

10: logic converter 20: amplifier

30: first comparison 40: second comparison

50: signal conversion unit 100: conversion circuit

TFA: Preamplifier for TTL logic signals AFA: Preamplifier for analog signals

OP1 to OP4: Comparators R1 to R6, RA, RB, RC, RD: Resistance

The present invention relates to a monitor, and more particularly, to an interface circuit of a monitor that converts a logic signal applied to the monitor into an analog signal.

As a signal applied to a high resolution monitor, an emitter coupled logic signal (hereinafter, referred to as an ECL logic signal) or an analog signal is widely used.

However, since such a monitor is a passive device for receiving a signal generated differently from a computer for generating a signal, a separate device capable of accommodating such an ECL logic signal and an analog signal is required.

A conventional monitor interface circuit for allowing a monitor to accept such a mechanized coupled logic signal and an analog signal is configured as shown in FIG. 1, and is applied through the pad P1 as in the pulse P1 of FIG. The negative ECL logic signal is converted by the logic converter 10 into a bipolar transistor-transistor logic signal (hereinafter referred to as a TTL logic signal) like the pulse P2.

The TTL logic signal output from the logic converter 10 is amplified by a TTL signal preamplifier (TFA) and the contrast is adjusted.

In addition, the analog signal applied through the pad P2, like the pulse P3, is amplified by the analog preamplifier AFA, and the contrast is controlled.

The signal amplified by the TTL logic signal amplifier (AFA) and the analog preamplifier (AFA) is amplified by the amplification unit 20, and then applied to the cathode of the rear cathode ray tube (CRT), thereby providing the cathode ray. The CRT can display a screen according to the ECL logic signal and the analog signal.

However, such a conventional monitor interface circuit requires an analog signal dedicated preamplifier in addition to a TTL signal dedicated preamplifier. Accordingly, a circuit for controlling contrast is used for the TTL signal dedicated preamplifier and analog signal dedicated preamplifier. It becomes necessary to compose the structure of the Hiro, there was a problem that can not be reduced in size and light weight.

This invention aims to solve this problem. The purpose of this invention is to convert an ECL signal into an analog signal, so that one can use a preamplifier and contrast control circuit and provide a monitor interface circuit that can be miniaturized and lightweight. have.

A feature of this invention for achieving this object is a conversion circuit for converting an input ECL logic signal into an analog signal, and connected to the conversion circuit to amplify an analog signal applied from the conversion circuit, And an amplifier circuit for controlling the analog signal preamplifier, the amplifying section connected to the first amplifier and amplifying the output of the analog signal preamplifier and applied to the cathode ray tube.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is an interface circuit diagram of a monitor according to the present invention, and includes a conversion circuit 100, an analog signal preamplifier (AFA), and an amplifier unit 20. As shown in FIG.

In more detail, the conversion circuit 100 includes the first and second comparison units 30, 40, and the signal conversion unit 50 as shown in FIG. 4, and the first comparison unit 30. ) Is a non-inverting terminal of the first ECL logic inversion signal (V1 bar) comparator (OP1) to the first ECL logic signal (V1) is applied to the comparator (OP1), the first ECL logic signal (V1) is inverted To be applied to (+).

In addition, the first comparator 30 allows the first ECL logic inversion signal V bar to be applied to the non-inverting terminal + of the comparator OP2, and pulls down a resistor for the inverting terminal of the comparator OP2. It is made to be applied to the reference voltage (-VB) through (R3).

In addition, the first comparator 30 has an impedance promoting resistance R1 connected between the inverting terminal (-) and the non-inverting terminal (+) of the comparator OP1. The reference voltage (-VB) is applied to the non-inverting terminal (+) of the comparators OP1 and OP2 through the pull-down resistor R2.

The second comparator 40 is made of the first comparator 30 in the same manner so that the second ECL logic signal V2 and the second ECL logic inverted signal V2 bar are comparators OP3 and OP4. Are compared and output from

In addition, in the signal converter 50 that adds the outputs of the first comparator 30 and the second comparator 40, the output of the comparator OP1 of the first comparator 20 is applied to the resistor R4. The output of the comparator OP2 of the first comparator 30 and the comparator OP3 of the second comparator 40 is applied to the resistor RB, and the output of the comparator OP4 is the resistor ( The signal conversion unit 50 is applied to RC) so that the outputs of the comparators OP1, OP2, OP3, and OP4 are summed and output.

In addition, an analog signal input to the conversion circuit 100 is amplified, while an analog signal preamplifier (AFA) capable of controlling contrast of a cathode ray tube configured at a rear end thereof is connected to the analog signal preamplifier ( By amplifying the signal input to AFA). The amplifier 20 is applied to the cathode ray tube (CRT).

Since the interface circuit of the monitor according to the present invention configured as described above is generated in four cases when the ECL logic signal applied to the conversion circuit 100 is two bits, the description will be divided into the first ECL logic signal V1 high level. In the first case applied to the first comparator 30 in a state, the first ECL logic inversion signal V1 bar is applied to the first comparator 30 in a low level state, so that the comparators OP1 and OP2 ) Outputs a high level signal.

In this case, when the second ECL logic signal V2 is also applied to the second comparator 40 as a logic signal in a high level state, the second ECL logic inversion signal V2 bar is in a low level state. Since it is applied to 40, the comparators OP3 and OP4 output logic signals in a high level state.

Therefore, the voltages of the high level state are all applied to the resistors RA, RB, and RC of the signal converter 50. The signal converter 50 outputs a voltage VO1 having a high level state.

The first comparator 30 receives a high level first ECL logic signal V1 and a first low level ECL logic inversion signal V1 bar, and inputs a low level to the second comparator 40. In the second case in which the second ECL logic signal V2 and the high level second ECL logic inversion signal V2 bar are input, the comparators OP1 and OP2 output a high level logic signal. (OP3) and (OP4) output a low level logic signal.

Therefore, a high level voltage is applied to the resistors RA and RB of the signal converter 50, and a low level voltage, that is, no voltage is applied to the resistor RC, so that the signal converter 50 is not applied. Output voltage (VO2) is

At this time, the output voltage VO3 becomes 67% of the output voltage VO1 in the first case.

The first ECL logic signal V1 is a logic signal of a low level counterpart, and the first ECL logic inversion signal V1 bar is applied to the first comparator 30 as a logic signal of a high level state. Third case where the second ECL logic signal V2 is a logic signal in a high level state and the second ECL logic inversion signal V2 bar is applied to the second comparator 40 as a logic signal in a low level state. The comparators OP1 and OP2 output low-level logic signals, and the comparators OP3 and OP4 output high-level logic signals.

Therefore, a high level voltage is applied to the resistor R8 of the signal converter 50, and the voltage of the low level state, that is, the voltage does not become long, to the resistors RA and RC. ) Output voltage (VO)

At this time, the output voltage Vo is 33% to the output voltage Vo1 in the first case.

The first ECL logic signal V1 is applied to the first comparator 30 as a logic signal in a low level state, and the first ECL logic inversion signal V1 bar is a logic signal in a high level state. When the second ECL logic signal V2 is a low level logic signal and the second ECL logic inversion signal V2 is applied to the second comparator 40 as a high level logic signal, the comparator (OP1), (OP2), (OP3), and (OP4) output low-level logic signals.

Therefore, since the low level voltage, that is, the voltage is not applied to the resistors RA, RB, and RC of the signal converter 50, the signal converter 50 has a low level voltage VO4. ), And the output voltage Vo4 at this time becomes 0% of the output voltage Vo1 in the first case.

This is shown in Table 1).

TABLE 1

In this way, the conversion circuit 100 compares the ECL logic signals in the first and second comparators 30 and 40, and then in the signal converter, the first and second comparators 30 and 40. By synthesizing the signals compared in, the digital signal ECL logic signal can be converted into an analog signal.

In FIG. 4, only the case of 2 bits is illustrated, but the number of bits can be extended by further configuring the comparison unit.

The analog signal output from the conversion circuit 100 and the analog signal applied through the terminal P2 are amplified by the analog signal preamplifier AFA, and the contrast is adjusted. ) Is applied to the cathode ray tube (CRT), the cathode ray tube (CRT) displays an image according to the ECL logic signal input through the terminal (P1) and the analog signal input through the terminal (P2). Done.

As described above, the interface circuit of the monitor according to the present invention converts an input ECL logic signal into an analog signal by using a conversion circuit so as to use an analog signal preamplifier and amplification unit in common with the input analog signal. This becomes simple and has the effect of being compact and lightweight.

Claims (4)

Conversion means for converting an input ECL logic signal into an analog signal, and connected to said conversion means to amplify an analog signal applied from said conversion means and an analog signal applied through a terminal (P2). It is connected to an analog signal preamplifier (AFA) for controlling contrast and the analog signal preamplifier (AFA) to amplify a signal applied from the analog signal preamplifier (AFA) and apply it to a cathode ray tube (CRT). An amplifier circuit (20), characterized in that the interface circuit of the monitor characterized by consisting of. The method of claim 1, wherein the converting means comprises: first and second comparison units 30 and 40 for comparing the input ECL logic signal to a reference voltage, the first and second comparison units 30, A monitor interface circuit comprising: a signal converter (50) for synthesizing an output of (40) and converting the output into an analog signal; The first comparator 30 and the second comparator 40 include a first ECL logic signal V1 and a second ECL logic signal V2. A monitor interface circuit comprising comparators (OP1), (OP2), (OP3), and (OP4) for comparison to V1 bar) and a second ECL logic inversion signal (V2 bar). The signal converter of claim 2, wherein the signal converter 50 includes a resistor RA connected to an output terminal of the comparator OP1 and a resistor connected to an output terminal of the comparisons OP2 and OP3. RB) and. And a resistor (RC) connected to an output terminal of the comparator (OP4) and the monitor circuit.