KR930000653Y1 - Dead picture-dot compensative apparatus - Google Patents

Abstract

No content.

Description

Dead pixel compensator

1 is a schematic diagram showing a schematic configuration of a dead pixel correction device according to the present invention.

Figure 2 is an exemplary embodiment of a memory means employed in the dead pixel correction device according to the present invention.

Figure 3 is an exemplary embodiment of a correction means employed in the dead pixel correction device according to the present invention.

4 is a waveform diagram showing waveforms appearing in each component of the dead pixel correction device according to the present invention.

* Explanation of symbols for main parts of the drawings

10: integration means 20: delay means

30: counter means 40: memory means

50: correction means 60: summing means

The present invention relates to a dead pixel correction device, and in particular, a dead pixel generated during the manufacturing process of a charge coupled device (CCD) used in a public video camera or an industrial camera is corrected. It relates to a dead pixel correction device that does not appear.

Generally, solid-state imaging devices called image sensors are classified into one-dimensional image sensors and two-dimensional image sensors. One-dimensional image sensors used in image scanners, fax machines, and copy machines are effective cameras when a subject moves at a constant speed. It is called a line sensor camera.

In addition, the two-dimensional image sensor, called an area (AREA) sensor, is a camera capable of capturing an image when a subject shifts variably.

The area sensor is classified into a frame transfer type CCD, an interline type CCD, and an MOS type imaging device according to a photoelectric changer for converting light into an electric signal and a method of transmitting the signal charge thereof. On the other hand, in the CCD used in the area sensor, a dead pixel is generated during the manufacturing process, and in order to prevent the dead pixel from appearing on the screen, the position of the dead pixel is conventionally stored in a memory device so that an image signal exists at the dead pixel position. Then, the dead pixels were corrected using a method of dividing the previous and previous horizontal pixels of the dead pixels stored in the memory device into two and then inserting an image signal. However, when the above method is used, the configuration of the dead pixel compensator is complicated, and there is a problem in that S / N and image quality are deteriorated.

Accordingly, an object of the present invention is to provide a dead pixel correction apparatus for correcting a dead pixel by adding an original image signal by detecting an image signal integrated at a dead pixel position as an object of the present invention.

In order to achieve the above object, the present invention provides an integration means for integrating and outputting an image signal with an arbitrary time constant, a delay means for delaying the image signal to a predetermined pitch value, and inputting vertical and horizontal driving pulse signals, respectively. A counter means for counting an address of a vertical or horizontal dead pixel position included in an integral signal output from said integrating means, memory means for storing an address value corresponding to the dead pixel position counted by said counter means, and said memory; The dead pixel is corrected by selecting one of the vertical or horizontal data signals outputted from the means and controlling the signal outputted from the integrating means to correct the dead pixels, the delay means and the signals outputted from the correction means, respectively. And summing means for outputting the normal video signal. The.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a schematic diagram showing a schematic configuration of a dead pixel correction device according to the present invention.

In FIG. 1, the integrating means 10 comprises a filter for integrating a video signal including a dead pixel signal with an arbitrary time constant, and the delay means 20 includes an image signal input to the integrating means 10. It is configured as a sample / hold circuit that receives a signal of the same property and delays the phase by about 0.5 pitch.

On the other hand, the counter means 30 comprises an address counter which inputs the vertical and horizontal driving pulse signals VD and HD to count the position of the vertical or horizontal dead pixels.

The memory means 40 has vertical and horizontal memories M1 and M2 for storing values corresponding to the dead pixel positions counted by the counter means 30, and an even number output from the vertical and horizontal memories M1 and M2. And first and second end gates G1 and G2 combining an odd number of vertical and horizontal data signals, respectively.

In addition, the correction means 50 receives the even and odd pixel data output from the memory means 40 and the even number transmitted from the memory means 40 as a level signal that changes when the dead pixel is even or odd. And a signal selection IC I1 for selecting odd pixel data and a MOS FET Q1 for inputting a signal selected by the signal selection IC I1 to a gate and passing an integrated signal output from the integration means 10. And an amplifier IC2 for amplifying the signals output from the MOS FET Q1 and the offset signals to the non-inverting terminal and the inverting terminal, respectively.

The summation means 60 is configured to add the video signals output from the delay means 20 and the correction means 50, respectively, to output a normal video signal in which the dead pixels are corrected.

Based on the above configuration, the present invention will be described in more detail.

In FIG. 1, when an image signal including a dead pixel signal is input to the integrating means 10 in the form of a waveform as shown in FIG. 4A, the integrating means 10 integrates the fourth b as a waveform to the correction means 50. Is sent. On the other hand, the counter means 30 controls the clock signal E having one cycle per one pixel (pitch), the vertical driving pulp F, and the horizontal driving pulse L, respectively, as shown in FIGS. 4E, 4F, and 4L. Also input in the form of a signal waveform to generate addresses D for vertical and horizontal memories. The address waveform as shown in FIG. 4D is input to the memory means 40 to supply an address to a two-bit memory in which the dead pixel positions are even and odd, and output data. That is, the vertical counter output signal A 'and the horizontal counter output signal B' are output from the output signal D of the counter means 30 as in the embodiment of the memory means 40 shown in FIG. The AND gate G1 is input to the vertical memory M1 and the horizontal memory M2, respectively, and the even and output data from the M1 and M2 are combined with the vertical and horizontal data values C 'and E', respectively. Output the signal waveform.

In addition, the AND gate G2 of FIG. 2 generates a signal as shown in FIG. 4I by combining odd-numbered vertical and horizontal data values D 'and F' output from the M1 and M2. The memory output even and odd signals H and I output from the AND gates G1 and G2 of the memory means 40 are It is input to the correction means 50 together with the pulses G and B signals. remind The pulse G is switched to the "high" and "low" signals, respectively, when an even or odd CCD screen is selected.

On the other hand, to the correction means 50 When the pulses G and B signals are input, as in the embodiment of the correction means 50 shown in FIG. 3, the signal selection IC IC1 converts one of the H and I signals to the MOS FET G1 by the G signal. ) To the gate. The data signal B output from the integrating means 10 is input to the non-inverting terminal (+) of the amplifier IC2 via the resistor R1. At this time, the amplifier IC2 is offset by the resistor R3 and the gain is set by the resistor R4 to cause an amplification effect. The signal from which the amplifier IC2 is output is a dead pixel correction data as a signal as shown in FIG. 4j.

On the other hand, the A signal of FIG. 4 is input to the delay means 20. The delay means 20 is for correcting the A signal as much as the dead pixel correction data is delayed, and thus can be achieved as a typical sample / hold circuit. The signal of FIG. 4C which is delayed by 0/5 pitch (0.5 pixel) by the delay means 20 is input to the adder 60 to be summed with the J signal, which is the correction data, to obtain a complete video signal K that does not include dead pixels. 4k is outputted in the same form as the waveform.

As described above, the present invention has an advantage in that S / N and image quality are excellent by correcting a dead pixel generated during the manufacturing process of a CCD used in public or industrial equipment such as a CCD camera to reproduce a complete image signal.

Claims (3)

An integrating means 10 for integrating and outputting a video signal with an arbitrary time constant, a delaying means 20 for delaying the video signal to a predetermined pitch value, and inputting vertical and horizontal driving pulse signals, respectively; A counter means 30 for counting addresses of vertical or horizontal dead pixel positions included in the integrated signal output from 10), and a memory for storing address values corresponding to the dead pixel positions counted by the counter means 30; Correction means (50) for correcting the dead pixels by selecting one of the means (40) and a vertical or horizontal data signal output from the memory means (40) and controlling the signal output from the integrating means (10), and And adding the signals output from the delay means 20 and the correction means 50 to the summing means 60 for outputting a normal video signal in which the dead pixels are corrected. Dead pixel correction device. 2. The memory device according to claim 1, wherein the memory means 40 comprises vertical and horizontal memories M1 and M2 for storing vertical and horizontal address values output from the counter means 20, and the vertical and horizontal memories M1 and M2. And AND gates (G1, G2) for combining the even and odd pixel data output from the < RTI ID = 0.0 >) < / RTI > to the correction means 50, respectively. 2. The signal selecting IC according to claim 1, wherein the correction means 50 selects even and odd enzyme data output from the memory means 40 as a level signal that changes when the position of the dead pixel is even or odd. IC1), a MOS FET Q1 for driving an integrated signal output from the integrating means 10 by transmitting a signal output from the signal selection IC IC1 to a gate, and outputting from the MOS FET Q1. And an amplifier (IC2) for amplifying the signal and the offset signal by inputting them to the non-inverting terminal and the inverting terminal, respectively.