KR920019102A - 2-stage subrange analog-to-digital converter - Google Patents

Abstract

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Description

2-stage subrange analog-to-digital converter

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2 is a schematic diagram showing a subrange ADC structure according to the present invention in which a single string of a transistor current source is used to generate a reference DAC bit current, a low resolution flash ADC reference ladder voltage, and an ADC dipole offset voltage;

FIG. 3 is a schematic diagram illustrating one embodiment of a FIG. 2 ADC device in which the low resolution flash ADC itself operates as a two-stage parallel subrange ADC and includes an internal DAC supplied by a single-column transistor current source with the same bit current.

Claims (19)

In subrange high resolution analog-to-digital converters, the converter consists of a reference voltage ladder constituting a series resistance connection, first converting the analog input signal and secondly converting the analog error signal into corresponding first and second low resolution digital signals. A low-resolution flash analog-to-digital converter for converting the current signal into a current output reference digital-to-analog converter having the same resolution as that of the low-resolution analog-to-digital converter; Error measuring means for measuring a difference between the analog feedback signal and the analog input signal for measurement, logic means for combining the first and second low resolution digital signals into a high resolution digital signal, and subsequently the first low resolution Digital signal, the An analog feedback signal, the analog error signal, the second low resolution digital signal and the timing-control means for generating the high resolution digital signal, wherein a single column of current sources controlled by the same servo circuit generate at least two reference currents. A two-stage subrange analog-to-digital converter characterized by being used. The analog-to-digital converter according to claim 1, wherein the subtraction resistance of the error measuring means, the resistance of the low resolution voltage reference ladder, and the current rising resistance of the servo circuit and the dipole offset resistance are all made of the same material. The analog-to-digital converter according to claim 2, wherein all the resistances of the reference voltage ladder have substantially the same resistance value. 4. The analog-digital converter as claimed in claim 3, wherein the single-row current source is constituted by a bipolar transistor junction structure driven by the same servo circuit. The maximum effective bit reference according to claim 1, wherein the low-resolution flash analog-digital converter configures a two-stage parallel subrange analog-digital converter, and the two-level parallel subrange analog-digital converter consists of a resistor connected in series. A maximum effective bit flash analog-digital converter configured to be a voltage ladder to generate a digital signal corresponding to the maximum significant bit of the first analog input signal and the second analog input signal, the resolution being the maximum bit flash analog-digital An internal digital-analog converter for reconverting a digital output to a corresponding analog feedback signal, an input to the maximum effective bit flash analog-digital converter and an analog feedback signal generated by the internal digital-analog converter Measure the analog difference between A subtractive resistor in the low resolution flash analog-digital transformer for the first analog input signal, comprising a subtractive resistor connected in series with a series resistor and a minimum effective bit reference voltage ladder connected in series with the maximum effective bit voltage ladder. And a minimum effective bit flash analog-to-digital converter for generating a digital signal corresponding to the minimum valid bit of the second analog error signal, and an output of the low resolution flash analog-to-digital converter. And logic means for combining the digital signal corresponding to the maximum valid bit and the minimum valid bit of the second analog error signal, wherein the single-row current source generates a bit current to be supplied to the internal digital-analog converter. Analog-to-digital conversion characterized by . The method of claim 5, wherein the error measuring means and the subtraction resistor of the low resolution flash analog-to-digital converter, the resistance of the reference digital-to-analog converter, the resistance of the maximum valid bit reference voltage ladder, and the minimum ubit reference voltage ladder Analog-to-digital converter, characterized in that both the resistor and the bipolar offset resistance is composed of the same material. The analog-to-digital converter according to claim 6, wherein each column of the series resistance string of the maximum valid bit and the minimum valid bit reference voltage ladder has the same resistance value. The method according to claim 7, wherein an equivalent value of the minimum valid bit reference voltage connected in series with the maximum valid bit reference voltage ladder is equal to a resistance value of each resistor connected in series with the maximum valid bit voltage ladder. Analog-to-digital converter. 9. The apparatus of claim 8, wherein the maximum effective bit flash analog-digital converter is configured as a 3-bit flash converter and the maximum effective bit flash analog-digital converter is configured as a 4-bit flash converter, the digital output of which is 7 -An analog-to-digital converter characterized in that it is combined to obtain a bit low resolution output. 10. The apparatus of claim 9, wherein the maximum effective bit and the minimum valid bit reference voltage ladder are configured with a series resistance string identical to the series resistance string, and are connected to a comparator string of the low resolution flash analog-digital converter so that both inputs of each comparator are input. And a bias current compensating circuit of said low resolution flash analog-to-digital converter configured to be exactly the same to cancel a bias current error. The analog-digital converter according to claim 10, wherein all the resistances of the bias current compensation circuit and all the resistances of the series resistance columns of the maximum valid bit and the minimum valid bit reference voltage ladder are the same and are made of the same material. . 12. The analog-digital converter as claimed in claim 11, wherein said single-row current source is comprised of a bipolar transistor junction structure composed of the same servo circuit. 12. An analog-digital converter as claimed in claim 11, wherein said single-row current source consists of a junction field effect transistor driven by the same servo circuit. 12. The analog-digital converter as claimed in claim 11, wherein said single column consists of a metal oxide semiconductor field transistor whose current source is driven by the same servo circuit. 12. An analog-digital converter as claimed in claim 11, wherein said single-row current source consists of a MOS transistor driven by the same servo circuit. 12. The analog-digital converter according to claim 11, wherein at least two of the reference currents consist of a current flowing through the reference voltage ladder of the low resolution flash analog-digital converter and a bit current of the reference digital-analog converter. 17. The analog to digital converter of claim 16, wherein at least two of said reference currents consist of a bit current of said internal digital to analog converter and a dipole offset current of a circuit. A method of converting an analog signal into a high resolution digital signal, the method comprising: a first low resolution digital signal corresponding to the upper significant bit of the high resolution digital signal through a low resolution flash analog-digital converter composed of a reference voltage ladder composed of a series resistance string; Passing an analog input signal to convert the first low resolution digital signal into a corresponding analog feedback signal; and converting the first low resolution digital signal into a corresponding analog feedback signal through a current output reference digital analog converter having the same resolution as that of the low resolution analog to digital converter. 1. Passing a low resolution digital signal, measuring a difference between the analog feedback signal and the analog input signal to measure an analog error signal, and a second low resolution digital signal corresponding to a lower significant bit of the high resolution digital signal. Passing the analog error signal through the low resolution flash analog-digital converter to convert the signal into a signal; combining the first and second low resolution digital signals into the high resolution digital signal; and a low resolution flash analog to digital converter. Providing a single-column current source to generate at least two currents among the current flowing through the reference voltage ladder, the bit current of the reference digital-analog converter and the dipole offset current of the circuit. How to convert to a signal. 19. The method of claim 18, wherein each pass through the low resolution flash analog-to-digital converter for first processing the analog input signal and then the analog signal corresponding to the analog error signal is a two-stage parallel subrange analog-to-digital conversion. And passing the analog through the low resolution flash analog to digital converter through a maximum significant bit flash analog to digital converter to further generate a first digital signal corresponding to the maximum significant bit of the analog signal. The first signal corresponding to the maximum significant bit of the analog signal through a current output internal digital-analog converter having the same resolution as the maximum effective bit flash analog-digital to reconvert the first digital signal to a corresponding analog internal feedback signal. 1 digit Passing a de-signal, generating an internal analog residual signal measured by the difference between the analog signal for the maximum effective bit flash analog-to-digital converter and the analog internal feedback signal generated by the internal digital-to-analog converter. Passing the internal analog residual signal through a minimum valid bit flash analog-to-digital converter to generate a second digital signal corresponding to the minimum valid bit of the analog signal; and for the internal digital to analog converter. Providing an additional current source to said single row of current sources to generate a bit current. ※ Note: The disclosure is based on the initial application.