KR920018737A - Digital PLL Circuit for CD - Google Patents

Digital PLL Circuit for CD Download PDF

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Publication number
KR920018737A
KR920018737A KR1019920003950A KR920003950A KR920018737A KR 920018737 A KR920018737 A KR 920018737A KR 1019920003950 A KR1019920003950 A KR 1019920003950A KR 920003950 A KR920003950 A KR 920003950A KR 920018737 A KR920018737 A KR 920018737A
Authority
KR
South Korea
Prior art keywords
pll circuit
digital pll
circuit
taton
lengths
Prior art date
Application number
KR1019920003950A
Other languages
Korean (ko)
Other versions
KR100240553B1 (en
Inventor
쇼조 마스다
가즈또시 시미즈메
Original Assignee
오오가 노리오
소니 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오오가 노리오, 소니 가부시끼가이샤 filed Critical 오오가 노리오
Publication of KR920018737A publication Critical patent/KR920018737A/en
Application granted granted Critical
Publication of KR100240553B1 publication Critical patent/KR100240553B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Optical Recording Or Reproduction (AREA)

Abstract

내용 없음No content

Description

CD용 디지털 PLL회로CD Digital PLL Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 한 실시예를 나타내는 CD용 디지털 PLL회로의 구성도,1 is a configuration diagram of a digital PLL circuit for a CD showing one embodiment of the present invention;

제2도는 본 발명의 CD용 디지털 PLL회로에 배치되는 주파수 계측 회로의 구성도,2 is a configuration diagram of a frequency measurement circuit disposed in the digital PLL circuit for CD of the present invention;

제3도는 비대칭을 설명하기 위한 개념도.3 is a conceptual diagram for explaining asymmetry.

Claims (1)

외부에서 주어진 콤팩트 디스크에서 재생된 EFM신호에 있어서의 각 태턴의 길이의 평균치를 산출해서 상기 각 패턴의 파형 길이를 결정하는 평균화 회로를 설치한 것을 특징으로 하는 CD용 디지털 PLL회로.A digital PLL circuit for a CD, characterized in that an averaging circuit is provided for calculating an average value of the lengths of each taton in an EFM signal reproduced from an externally provided compact disc to determine the waveform length of each pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920003950A 1991-03-13 1992-03-11 Digital pll circuit for cd KR100240553B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-74111 1991-03-13
JP07411191A JP3225530B2 (en) 1991-03-13 1991-03-13 Digital PLL circuit for CD

Publications (2)

Publication Number Publication Date
KR920018737A true KR920018737A (en) 1992-10-22
KR100240553B1 KR100240553B1 (en) 2000-01-15

Family

ID=13537763

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920003950A KR100240553B1 (en) 1991-03-13 1992-03-11 Digital pll circuit for cd

Country Status (2)

Country Link
JP (1) JP3225530B2 (en)
KR (1) KR100240553B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2518148B2 (en) * 1993-03-12 1996-07-24 日本電気株式会社 Clock dependent synchronization method

Also Published As

Publication number Publication date
KR100240553B1 (en) 2000-01-15
JP3225530B2 (en) 2001-11-05
JPH04285771A (en) 1992-10-09

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