KR920013896A - Automatic Gain Control Circuit - Google Patents

Automatic Gain Control Circuit Download PDF

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Publication number
KR920013896A
KR920013896A KR1019900021228A KR900021228A KR920013896A KR 920013896 A KR920013896 A KR 920013896A KR 1019900021228 A KR1019900021228 A KR 1019900021228A KR 900021228 A KR900021228 A KR 900021228A KR 920013896 A KR920013896 A KR 920013896A
Authority
KR
South Korea
Prior art keywords
frame pulse
level
detecting
low
automatic gain
Prior art date
Application number
KR1019900021228A
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Korean (ko)
Other versions
KR0160118B1 (en
Inventor
이태희
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019900021228A priority Critical patent/KR0160118B1/en
Publication of KR920013896A publication Critical patent/KR920013896A/en
Application granted granted Critical
Publication of KR0160118B1 publication Critical patent/KR0160118B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control

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  • Television Systems (AREA)
  • Television Receiver Circuits (AREA)
  • Picture Signal Circuits (AREA)

Abstract

내용 없음No content

Description

자동이득조절회로Automatic Gain Control Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 자동이득조절회로의 전체구성블럭도, 제2도는 제1도의 자동이득조절회로의 상세회로도.1 is an overall configuration block diagram of the automatic gain control circuit according to the present invention, and FIG. 2 is a detailed circuit diagram of the automatic gain control circuit of FIG.

Claims (3)

입력되는 아날로그 뮤즈신호를 디지탈신호로 양자화하는 A/D변환수단과, 상기 디지탈뮤즈신호중 프레임펄스의 하이/로우 레벨간의 레벨차를 검출하는 레벨차 검출수단과, 규정프레임펄스의 레벨과 입력프레임펄스의 레벨을 비교하여 실제 자동이득 조절에 소요되는 레벨변동분을 검출하는 보상치 검출수단과, 상기 검출된 소요레벨을 A/D변환해서 아날로그 형태의 소요레벨에 따라 D/A변환수단의 기준전압을 가변하는 제어수단을 포함함을 특징으로 하는 자동이득조절회로.A / D conversion means for quantizing the input analog muse signal into a digital signal, level difference detecting means for detecting a level difference between high and low levels of frame pulses in the digital muse signal, level of a prescribed frame pulse and input frame pulse Compensation value detection means for detecting the level fluctuation required for the actual automatic gain adjustment by comparing the levels of A and A, and converting the detected required level to the reference voltage of the D / A conversion means according to the required level in analog form. Automatic gain control circuit comprising a variable control means. 제1항에 있어서, 상기 레벨차검출수단은 수평/수직방향으로 프레임 펄스구간을 검출하는 프레임펄스마스크부와, 프레임펄스중 하이/로우 저속기간을 검출하는 프레임펄스 윈도우부와, 상기 프레임펄스 마스크부 및 상기 프레임펄스윈도우부의 검출신호로부터 프레임펄스의 하이/로우레벨을 검출하는 프레임펄스 H/L 레벨검출부와, 상기 프레임펄스 하이/로우레벨을 딜레이소자를 이용해 소정시간마큼 지연시켜서 프레임펄스의 하이/로우 레벨간의 레벨차를 구하는 프레임펄스 레벨차 검출부를 포함함을 특징으로 하는 자동이득 조절회로.2. The apparatus of claim 1, wherein the level difference detecting means comprises: a frame pulse mask portion for detecting a frame pulse section in a horizontal / vertical direction, a frame pulse window portion for detecting a high / low low speed period among frame pulses, and the frame pulse mask A frame pulse H / L level detection unit for detecting a high / low level of the frame pulse from the detection signal of the unit and the frame pulse window unit, and the frame pulse high / low level is delayed for a predetermined time by using a delay element. And a frame pulse level difference detector for obtaining a level difference between the low and low levels. 제1항에 있어서, 보상치검출수단은 규정 프레임펄스레벨과 입력 프레임펄스레벨간의 대.소를 비교하는 비교부와, 입력 프레임펄스와 규정 프레임펄스간의 차분을 검출하기 위한 감산기로 구성되어 있는 소요레벨검출부를 포함함을 특징으로 하는 자동이득조절회로.2. The compensation value detecting means according to claim 1, wherein the compensation value detecting means comprises a comparator for comparing the size between the specified frame pulse level and the input frame pulse level, and a subtractor for detecting the difference between the input frame pulse and the specified frame pulse. Automatic gain control circuit comprising a level detection unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021228A 1990-12-20 1990-12-20 Automatic gain controlling circuit KR0160118B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021228A KR0160118B1 (en) 1990-12-20 1990-12-20 Automatic gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021228A KR0160118B1 (en) 1990-12-20 1990-12-20 Automatic gain controlling circuit

Publications (2)

Publication Number Publication Date
KR920013896A true KR920013896A (en) 1992-07-30
KR0160118B1 KR0160118B1 (en) 1999-03-20

Family

ID=19308007

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021228A KR0160118B1 (en) 1990-12-20 1990-12-20 Automatic gain controlling circuit

Country Status (1)

Country Link
KR (1) KR0160118B1 (en)

Also Published As

Publication number Publication date
KR0160118B1 (en) 1999-03-20

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