KR920013171A - Processor Array Architecture for Neural Networks - Google Patents

Processor Array Architecture for Neural Networks Download PDF

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Publication number
KR920013171A
KR920013171A KR1019900021850A KR900021850A KR920013171A KR 920013171 A KR920013171 A KR 920013171A KR 1019900021850 A KR1019900021850 A KR 1019900021850A KR 900021850 A KR900021850 A KR 900021850A KR 920013171 A KR920013171 A KR 920013171A
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KR
South Korea
Prior art keywords
neural networks
processor array
array architecture
ring
mesh structure
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KR1019900021850A
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Korean (ko)
Inventor
이훈복
김종문
박신종
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900021850A priority Critical patent/KR920013171A/en
Publication of KR920013171A publication Critical patent/KR920013171A/en

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Abstract

내용 없음No content

Description

신경회로망을 위한 프로세서 어레이 구조Processor Array Architecture for Neural Networks

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 역전파학습 신경회로망의 컴퓨테이션 그래프, 제2도는 본 발명의 프로세싱 노드들과 통신 노드들로 이루어진 프로세서 어레이구조를 나타낸 개략도, 제3도는 2-layer역전파학습 신경회로망을 프로세서 어레이에맵핑(mapping)한 상태를 나타낸 개략도.1 is a computational graph of a backpropagation neural network, FIG. 2 is a schematic diagram showing a processor array structure consisting of processing nodes and communication nodes of the present invention, and FIG. 3 is a two-layer backpropagation neural network connected to a processor array. Schematic diagram of the mapped state.

Claims (1)

2차원 메쉬구조로 연결된 프로세싱노드(PN)들은 링구조를 위한 링연결과 2차원 메쉬구조의 피드백(feedback)의 연결형태를 가지면서 우측의 스위칭노드(CN)들을 통하여 외부와의 데이타 입출력을 수행하도록 구성됨을 특징으로 하는 신경회로망을 위한 프로세서 어레이구조.The processing nodes PN connected by the 2D mesh structure have a ring connection for the ring structure and a feedback connection of the 2D mesh structure, and perform data input / output with the outside through the switching nodes CN on the right side. And a processor array structure for neural networks. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021850A 1990-12-26 1990-12-26 Processor Array Architecture for Neural Networks KR920013171A (en)

Priority Applications (1)

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KR1019900021850A KR920013171A (en) 1990-12-26 1990-12-26 Processor Array Architecture for Neural Networks

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Application Number Priority Date Filing Date Title
KR1019900021850A KR920013171A (en) 1990-12-26 1990-12-26 Processor Array Architecture for Neural Networks

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KR920013171A true KR920013171A (en) 1992-07-28

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KR1019900021850A KR920013171A (en) 1990-12-26 1990-12-26 Processor Array Architecture for Neural Networks

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11093439B2 (en) 2017-10-31 2021-08-17 Samsung Electronics Co., Ltd. Processor and control methods thereof for performing deep learning

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11093439B2 (en) 2017-10-31 2021-08-17 Samsung Electronics Co., Ltd. Processor and control methods thereof for performing deep learning

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