KR920013063A - Acceleration / Deceleration Pattern Generation Circuit and Method - Google Patents

Abstract

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Description

Acceleration / Deceleration Pattern Generation Circuit and Method

Since this is an open matter, no full text was included.

2 is a pattern diagram of a trapezoidal acceleration / deceleration pattern generator, and FIG. 3 is a block diagram showing the configuration of the trapezoidal acceleration / deceleration pattern generator according to the present invention, and FIG. 4 is a flowchart showing the operation procedure of the present invention.

Claims (2)

The latch circuit 1 to which the reference speed data is input, the comparator 2 for comparing the output data D _A of the latch circuit 1 and the output data D _B of the up-down counter, and the data ( A central processing unit (CPU) 5 which outputs D _B ) and provides a clock to the up-down counter 3 operated by the control signals C ₁ and C ₂ of the comparator; And a multiplexer (4) for generating an output frequency based on an input frequency and data (D _B ) of the up-down counter. Data to set the initial value (V _R) to the comparator 2 through the latch circuit 1, a comparator (2) the data (D _B) by the up-down counter (3) for entering (D _A), and operates by the clock Input to the multiplexer (4), the comparator compares the data (D _A, D _B ) and down counts by the control signal (C ₁ ) (H) if D _{A <} D _B , and controls if D _A = D _B By stopping the operation of the up-down counter 3 by the signal C ₂ (H), the output frequency fout is outputted. When the time T ₂ is reached and t = T ₂ , the initial value V _R is again obtained. And setting the control signal (C ₁ ) high (H) to end the operation of the up-down counter. ※ Note: The disclosure is based on the initial application.