KR920011426A - Bus Monitor for Cache Memory Control - Google Patents

Bus Monitor for Cache Memory Control Download PDF

Info

Publication number
KR920011426A
KR920011426A KR1019900021844A KR900021844A KR920011426A KR 920011426 A KR920011426 A KR 920011426A KR 1019900021844 A KR1019900021844 A KR 1019900021844A KR 900021844 A KR900021844 A KR 900021844A KR 920011426 A KR920011426 A KR 920011426A
Authority
KR
South Korea
Prior art keywords
snoop
memory
update
wrb
signal
Prior art date
Application number
KR1019900021844A
Other languages
Korean (ko)
Other versions
KR930003991B1 (en
Inventor
김기영
김성운
김용연
윤용호
천유식
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019900021844A priority Critical patent/KR930003991B1/en
Publication of KR920011426A publication Critical patent/KR920011426A/en
Application granted granted Critical
Publication of KR930003991B1 publication Critical patent/KR930003991B1/en

Links

Classifications

    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L7/00—Suction cleaners adapted for additional purposes; Tables with suction openings for cleaning purposes; Containers for cleaning articles by suction; Suction cleaners adapted to cleaning of brushes; Suction cleaners adapted to taking-up liquids
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Abstract

내용 없음No content

Description

캐쉬메모리 제어를 위한 버스 감시장치Bus Monitor for Cache Memory Control

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 캐쉬메모리 제어를 위한 버스 감시장치의 블록 다이어그램, 제2도는 본 발명의 캐쉬메모리 제어를 위한 버스 감시장치의 상세 신호도, 제3도는 본 발명 회로의 일부분인 WT의 흐름도.1 is a block diagram of a bus monitoring apparatus for cache memory control of the present invention, FIG. 2 is a detailed signal diagram of a bus monitoring apparatus for cache memory control of the present invention, and FIG. 3 is a flowchart of a WT which is a part of the circuit of the present invention.

Claims (1)

라이트백모드를 사용하는 다수의 캐쉬메모리를 제어하기 위한 버스감시장치에 있어서 스누우프 메모리의 내용에 따라 라이트백신호(WRB), 업데이트신호(UPDATE)등을 만들면서 캐쉬메모리의 입력상태도 만드는 스누우프메모리 데이터경로설정기(13)와, 상기 스누우프 메모리데이타경로 설정기(13)의 출력신호(WRB)(UPDATE)에 따라 제어신호(DIRTY), (SHD), (SNACK)를 만드는 시스템버스 감시기(11)와, 상기 스누우프 메모리데이타경로 설정기(13)의 출력신호(UPDATE)에 의해 스누우프 상태메모리와 스누우프 테그 메모리의 쓰기 신호(WB)를 만드는 스누우프 메모리제어기(14)와, 상기 스누우프 메모리데이타 경로설정기(13)의 출력 신호(SD-WRB)에 의해 상기 시스템 버스요청기(12)에 시스템 버스의 사용을 요청하는 스누우프 요청기(12)들로 구성됨을 특징으로 하는 캐쉬메모리제어를 위한 버스감시장치.A bus monitoring device for controlling multiple cache memories using the writeback mode, which generates a writeback signal (WRB), an update signal (UPDATE), etc. according to the contents of a snoop memory, and also a cache memory input state. The control signals DIRTY, SHD, and SNACK are generated according to the output signal WRB (UPDATE) of the snoop memory data path setter 13 and the snoop memory data path setter 13. A snoop that produces a snoop state memory and a snoop tag memory write signal (WB) by means of an output signal UPDATE of the system bus monitor 11 and the snoop memory data path setter 13. A snoop requester for requesting the system bus requester 12 to use the system bus by means of a memory controller 14 and an output signal SD-WRB of the snoop memory data routing device 13. Cache memory, characterized in that consists of 12 Bus monitoring system for air. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021844A 1990-12-26 1990-12-26 Bus snooper for controlling cache memory KR930003991B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021844A KR930003991B1 (en) 1990-12-26 1990-12-26 Bus snooper for controlling cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021844A KR930003991B1 (en) 1990-12-26 1990-12-26 Bus snooper for controlling cache memory

Publications (2)

Publication Number Publication Date
KR920011426A true KR920011426A (en) 1992-07-24
KR930003991B1 KR930003991B1 (en) 1993-05-19

Family

ID=19308521

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021844A KR930003991B1 (en) 1990-12-26 1990-12-26 Bus snooper for controlling cache memory

Country Status (1)

Country Link
KR (1) KR930003991B1 (en)

Also Published As

Publication number Publication date
KR930003991B1 (en) 1993-05-19

Similar Documents

Publication Publication Date Title
KR950029941A (en) Snooze Circuit in Multiprocessor System
KR890017609A (en) Multiprocessor Data Processing System and Cache Device Used in It
KR910003498A (en) Microprocessor
KR930010742A (en) Memory access device
KR920013460A (en) Output control circuit of sense amplifier
KR880011676A (en) Block access method using cache memory
KR950009444A (en) Cache Consistency Method and Cache Consistency Data Processing System
KR960024986A (en) Information processing device
KR950029886A (en) Control system
KR920011426A (en) Bus Monitor for Cache Memory Control
KR960025112A (en) System apparatus and method in which multiple processors share one cache memory
KR940000976A (en) Booting Method and Device of Multiprocessor System
ATE175287T1 (en) SIGNAL PROCESSOR
KR900006844A (en) I / O device of operation control device
KR910001566A (en) Common Memory Access
KR970016898A (en) Data processor and access method
KR930001069A (en) Directly Controlled Cache Memory
KR890013567A (en) Direct Memory Access Control
KR950020230A (en) Memory Sharing Access Control Unit in Multiprocessor System
KR940009853A (en) Bus Operation Control Method for Cache Aggregation of Travel Computing Network System (TICOM)
KR920013126A (en) Cache memory control circuit
KR940000990A (en) Multiprocessor System with Bus Handler
KR940015840A (en) Homogeneity Guarantee Device and Method of Two Level Cache Memory
KR920010385A (en) Programmable Logic Controller Circuit
KR970012172A (en) BUS CONTROLLER DEVICE FOR MULTI-Microprocessors

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19980313

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee