KR920010953A - Single layer high electron mobility transistor and manufacturing method thereof - Google Patents

Abstract

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Description

Single layer high conductivity transistor and its manufacturing method

Since this is an open matter, no full text was included.

3 is a perspective view showing the structure of a single-layer HEMT according to the present invention.

Claims (7)

On the semi-insulating substrate, there is a laminated structure of an active layer made of a first compound semiconductor having a small energy band gap without doping impurities, and a letter supply layer made of a second compound semiconductor having a large energy band gap doped with impurities. On the electron supply layer of the source and drain regions, the source and drain electrodes have a source and drain electrodes on the electron supply layer of the first compound semiconductor doped with impurities and are defined between the source and drain regions. A high electron mobility transistor having a gate electrode and a two-dimensional electron gas layer generated in an active layer near a heterojunction interface of the electron supply layer and an active layer as a conductive channel between a source and a drain, wherein the cap layer thickness of the source and drain regions The channel such that the two-dimensional electron gas layer of the channel region is horizontally aligned within the channel region Wherein the power of the reverse surface of the thermoformable substrate single-layered high electron mobility, characterized in that having a high structure than the surface of the semi-insulating substrate in the source and drain regions also transistor. The single-layer high electron mobility transistor according to claim 1, wherein the first compound semiconductor is GaAs and the second compound semiconductor is AlGaAs. The single-layer high electron mobility transistor according to claim 1, further comprising a spacer layer comprising a semiconductor comprising a second compound which is not doped with impurities between the electron supply weight and the active layer. The method of claim 3, wherein the difference between the surface heights of the semi-insulating substrates of the channel region and the source and drain regions is greater than the sum of the thicknesses of the spacer layer and the electron supply layer, and the sum of the thicknesses of the spacer layer, the electron supply layer, and the cap layer. Single layer high electron mobility transistor, characterized in that smaller than. An active layer composed of a first compound semiconductor having a small energy band gap without being doped with impurities, and an electron supply layer made of a second compound semiconductor having a large energy band gap with an impurity formed thereon, The electron supply layer of the source and drain regions is formed on the electron supply layer of the channel region defined between the source and drain regions with a source and drain electrode interposed between the source and drain electrodes through a cap layer of the first compound semiconductor doped with impurities. A method of manufacturing a high electron mobility transistor having a gate electrode and a two-dimensional electron gas layer generated in an active layer near the heterojunction interface of the electron supply layer and the active charge as a conductive channel between a source and a drain, except for the channel region. Etching the insulating substrate in the source and drain regions to a predetermined depth, wherein the equation Sequentially growing the active layer, the electron supply layer, and the cap layer on the etched semi-insulating substrate by a conventional compound semiconductor epitaxial growth method after jade crystals; removing the cap layer of the channel region after the growth process; And a process of forming a gate electrode rate, a source and a drain region in the channel region and a source and a drain electrode in the channel region after the second process, respectively. The single layer high electron mobility transistor according to claim 5, wherein the etching depth of the etching process has a depth such that the two-dimensional electron gas layer of the channel region is horizontally aligned with the cap layer of the source and drain regions. Manufacturing method. 6. The method of claim 5, wherein the compound semiconductor epitaxial growth method is any one of a molecular beam epitaxial growth method and a metal-organic chemical intermediate deposition growth method. ※ Note: It is disclosed by the contents of the initial application.