KR920010876A - Method for forming metal layer contact on polysilicon layer - Google Patents

Method for forming metal layer contact on polysilicon layer Download PDF

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Publication number
KR920010876A
KR920010876A KR1019900018090A KR900018090A KR920010876A KR 920010876 A KR920010876 A KR 920010876A KR 1019900018090 A KR1019900018090 A KR 1019900018090A KR 900018090 A KR900018090 A KR 900018090A KR 920010876 A KR920010876 A KR 920010876A
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KR
South Korea
Prior art keywords
layer
forming
polysilicon layer
polysilicon
via hole
Prior art date
Application number
KR1019900018090A
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Korean (ko)
Other versions
KR930008871B1 (en
Inventor
오춘식
이신국
이종호
김창남
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019900018090A priority Critical patent/KR930008871B1/en
Publication of KR920010876A publication Critical patent/KR920010876A/en
Application granted granted Critical
Publication of KR930008871B1 publication Critical patent/KR930008871B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

폴리실리콘층에 금속층 콘택 형성방법Method for forming metal layer contact on polysilicon layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의해 금속층이 제1폴리실리콘층에 접속되고 제1폴리실리콘 하부에 비아콘택시킨 제2폴리실리콘층을 형성한 상태의 단면도.2 is a cross-sectional view of a state in which a metal layer is connected to a first polysilicon layer according to the present invention, and a second polysilicon layer is formed by via contacting under the first polysilicon.

Claims (3)

폴리실리콘층에 금속층 콘택 형성방법에 있어서, 소정의 물질층 소정상부에 제2폴리실리콘층을 소정의 물질층 소정상부에 제2폴리실리콘층을 형성하고, 제2폴리실리콘층을 포함하는 전영역 상부에 제1절연층을 형성하는 단계와, 상기 제2폴리실리콘층 상부의 제1절연층을 소정부분 제거하여 비아 홀(Via hole)을 형성하는 단계와, 상기 비아홀을 포함하는 소정부분에 제1폴리실리콘층을 형성하여 제2폴리실리콘층에 접속한 다음, 전체적으로 제2절연층을 형성하는 단계와, 상기 비아홀 상부의 제2절연층을 소정부분 제거하여 콘택홀을 형성하고 소정부분에 금속층을 형성하여 제1폴리실리콘에 접속하는 단계로 이루어지는 것을 특징으로 하는 폴리실리콘층에 금속층 콘택형성방법.A method for forming a metal layer contact on a polysilicon layer, comprising: forming a second polysilicon layer on a predetermined material layer on a predetermined material layer, and forming a second polysilicon layer on a predetermined material layer on a predetermined material layer, and including a second polysilicon layer Forming a via hole by forming a first insulating layer thereon, removing a predetermined portion of the first insulating layer on the second polysilicon layer, and forming a via hole in the predetermined part including the via hole; Forming a polysilicon layer and connecting it to the second polysilicon layer, and then forming a second insulating layer as a whole; forming a contact hole by removing a predetermined portion of the second insulating layer over the via hole, and forming a metal layer at the predetermined portion. Forming a metal layer and contacting the first polysilicon; 제1항에 있어서, 상기 콘택홀을 비아홀 상부에 위치하며, 비아홀의 면적보다 작게 형성하는 것을 특징으로 하는 폴리실리콘층에 금속층 콘택형성방법.The method of claim 1, wherein the contact hole is positioned above the via hole and is formed to be smaller than the area of the via hole. 제1항에 있어서, 상기 제1폴리실리콘층 대신에 폴리사이드(Polycide)를 형성하는 것을 특징으로 하는 폴리실리콘층에 금속층 콘택형성방법.The method of claim 1, wherein a polycide is formed in place of the first polysilicon layer. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900018090A 1990-11-09 1990-11-09 Metal layer contact forming method KR930008871B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900018090A KR930008871B1 (en) 1990-11-09 1990-11-09 Metal layer contact forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018090A KR930008871B1 (en) 1990-11-09 1990-11-09 Metal layer contact forming method

Publications (2)

Publication Number Publication Date
KR920010876A true KR920010876A (en) 1992-06-27
KR930008871B1 KR930008871B1 (en) 1993-09-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018090A KR930008871B1 (en) 1990-11-09 1990-11-09 Metal layer contact forming method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140115814A (en) * 2013-03-22 2014-10-01 삼성전자주식회사 Substrate assembly, method of forming the substrate assembly, and electronic device comprising the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140115814A (en) * 2013-03-22 2014-10-01 삼성전자주식회사 Substrate assembly, method of forming the substrate assembly, and electronic device comprising the same

Also Published As

Publication number Publication date
KR930008871B1 (en) 1993-09-16

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