KR920008610A - Data communication system and communication method - Google Patents

Data communication system and communication method Download PDF

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Publication number
KR920008610A
KR920008610A KR1019900016572A KR900016572A KR920008610A KR 920008610 A KR920008610 A KR 920008610A KR 1019900016572 A KR1019900016572 A KR 1019900016572A KR 900016572 A KR900016572 A KR 900016572A KR 920008610 A KR920008610 A KR 920008610A
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South Korea
Prior art keywords
data
processor
transceiver
processors
communication system
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KR1019900016572A
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Korean (ko)
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KR930004903B1 (en
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강희택
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정몽헌
현대전자산업 주식회사
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Priority to KR1019900016572A priority Critical patent/KR930004903B1/en
Publication of KR920008610A publication Critical patent/KR920008610A/en
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Publication of KR930004903B1 publication Critical patent/KR930004903B1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M9/00Arrangements for interconnection not involving centralised switching
    • H04M9/002Arrangements for interconnection not involving centralised switching with subscriber controlled access to a line, i.e. key telephone systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)

Abstract

내용 없음No content

Description

데이타 통신시스팀 및 통신방법Data communication system and communication method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 데이타 통신시스팀의 구성도.1 is a block diagram of a data communication system according to the present invention.

제2도는 본 발명에 의한 데이타 통신방법법의 흐름도.2 is a flowchart of a data communication method method according to the present invention.

Claims (4)

제1 및 제2프로세서(1,2)간의 데이타를 교환하기 위한 데이타 통신시스팀에 있어서; 상기 제1프로세서(1)에 연결되어 데이타를 병렬로 전송하기 위한 데이타버스, 상기 데이타 버스에 연결되어 전송할 데이타를 일시적으로 저장하는 데이타 트랜시버(3), 상기 제2프로세서(2) 및 데이타 트랜시버(3)에 연결되어 데이타를 병렬로 전송하기 위한 데이타 버스, 및 상기 제1 및 제2프로세서(1,2)및 데이타 트랜시버(3)에 연결되어 상기 제1 및 제2프로세서(1,2)의 처리 상태를 제어하는 플립플롭(4,5)으로 구성되는 것을 특징으로 하는 데이타 통신 시스팀.A data communication system for exchanging data between first and second processors (1, 2); A data bus connected to the first processor 1 for transmitting data in parallel, a data transceiver 3 connected to the data bus to temporarily store data to be transmitted, the second processor 2 and a data transceiver ( 3) a data bus for transmitting data in parallel, and the first and second processors 1 and 2 and the data transceiver 3 to connect the first and second processors 1 and 2, respectively. A data communication system, comprising a flip-flop (4, 5) for controlling the processing state. 제1및 제2프로세서(1,2), 상기 제1프로세서(1)에 연결되어 데이타를 병렬로 전송하기 위한 데이타 버스, 상기 데이타 버스에 연결되어 전송할 데이타를 일시적으로 저장하는 데이타 트랜시버(3), 상기 제2프로세서(2)및 데이타 트랜시버(3)에 연결되어 데이타를 병렬로 전송하기 위한 데이타 버스, 및 상기 제1 및 제2프로세서(1,2) 및 데이타 트랜시버(3)에 연결되어 상기 제1 및 제2프로세서(1,2)의 처리상태를 제어하는 플립플롭(4,5)을 포함하여 구성되는 데이타 통신시스팀의 통신방법에 있어서; 상기 제1프로세서(1)에 내부 인터럽트가 서비스되는 제1단계, 상기 제1프로세서(1)에서 상기 제2프로세서(2)로 데이타를 전송하는 제2단계, 및 상기 제2프로세서(2)에서 상기 제1프로세서(1)로 데이타를 전송하는 제3단계에 의해 수행되는 것을 특징으로 하는 데이타 통신방법.First and second processors (1 and 2), a data bus (3) connected to the first processor (1) for transmitting data in parallel, and a data transceiver (3) for temporarily storing data to be connected to the data bus for transmission. A data bus connected to the second processor 2 and the data transceiver 3 to transmit data in parallel, and connected to the first and second processors 1 and 2 and the data transceiver 3 A communication method of a data communication system, comprising: flip-flops (4, 5) for controlling processing states of first and second processors (1, 2); A first step in which an internal interrupt is serviced to the first processor 1, a second step of transferring data from the first processor 1 to the second processor 2, and at the second processor 2 And a third step of transmitting data to said first processor (1). 제2항에 있어서, 상기 제2단계는 상기 제2프로세서(2)로 전송할 데이타를 상기 데이타 트랜시버(3)에 일시적으로 기억시키는 제1단계, 상기 제2프로세서(2)의 인터럽트 루틴이 서비스되어 상기 데이타를 읽어 들이는 제2단계, 및 상기 데이타가 마지막 메시지인지 검색하여 마지막 메시지가 될때까지 상기 제1 및 제2단계를 반복하여 처리하는 제3단계에 의해 수행되는 것을 특징으로 하는 데이타 통신방법.3. The method of claim 2, wherein the second step is a first step of temporarily storing data to be transmitted to the second processor 2 in the data transceiver 3, and an interrupt routine of the second processor 2 is serviced. A second step of reading the data, and a third step of searching for whether the data is the last message and repeatedly processing the first and second steps until the last message is obtained. . 제2항에 있어서, 상기 제3단계는 상기 프로세서(1)로 전송할 데이타를 상기 데이타 트랜시버(3)에 일시적으로 기억시키는 제1단계, 상기 프로세서(1)가 데이타를 읽어 지정된 메모리에 저장하는 제2단계, 및 상기 데이타가 마지막 메시지인지 검색하여 마지막 메시지가 될때까지 상기 제1 및 제2단계를 반복하여 처리하는 제3단계에 의해 수행되는 것을 특징으로 하는 데이타 통신방법.3. The method of claim 2, wherein the third step includes a first step of temporarily storing data to be transmitted to the processor 1 in the data transceiver 3, and a method in which the processor 1 reads data and stores the data in a designated memory. And a third step of searching for whether the data is the last message and repeatedly processing the first and second steps until the last message is obtained. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900016572A 1990-10-18 1990-10-18 Parallel data communication system and its method between processors by using data bus KR930004903B1 (en)

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KR1019900016572A KR930004903B1 (en) 1990-10-18 1990-10-18 Parallel data communication system and its method between processors by using data bus

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Application Number Priority Date Filing Date Title
KR1019900016572A KR930004903B1 (en) 1990-10-18 1990-10-18 Parallel data communication system and its method between processors by using data bus

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KR920008610A true KR920008610A (en) 1992-05-28
KR930004903B1 KR930004903B1 (en) 1993-06-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382845B1 (en) * 2000-12-08 2003-05-09 박종덕 Vacuum abstraction method of the medicinal herb

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382845B1 (en) * 2000-12-08 2003-05-09 박종덕 Vacuum abstraction method of the medicinal herb

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KR930004903B1 (en) 1993-06-10

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