KR920008241B1 - A circuit which controls dot matrix and the control method - Google Patents

Abstract

A circuit controlls the recess time in the duty cycle and selectively drives the multi-color LED dot matrix display. The reset signals (CLK,LAT,R,G,A-D) except the red and green data signals (RD,GD) are provided to a 4 x 16 column decoder (23) through two buffers (21,22). The decoded outputs of the 4 x 16 column decoder are provided to a red/green 16 x 16 dot matrix circuit (25) through a dot matrix driving circuit (24). One terminal of the 16 x 16 dot matrix circuit is connected with two 8 bit registers (26,27) coupled with the red data signal, and another terminal is connected with two 8 bit registers (30,31) coupled with the green data signal.

Description

Control circuit and control method of LED dot matrix

1 is a block diagram showing a display device of the prior art.

2 is a detailed circuit diagram constructed in accordance with the principles of the present invention.

* Explanation of symbols for main parts of the drawings

1: First switch circuit 2, 3: Shift register

4: current amplifier circuit 5: second switch circuit

5, 6: Counter 8: Decoder

The present invention relates to an LED dot matrix control circuit and method, and more particularly to a LED dot matrix control circuit and a method of driving an LED dot matrix in order to express a multi-color at high speed by driving the LED dot matrix as a dynamic driving method. Dynamic (Time Division, Multi-Clex) driving and dynamic driving are largely classified.

In the case of the dot matrix driving, a dynamic driving method is generally adopted to simplify the driving circuit except when the number of pixels is small.

However, in the dynamic driving method, when voltage is applied to each column and row of the positive and negative poles of a predetermined pixel, a predetermined voltage is generated at the drive selection pixel, and at the same time, an equivalent voltage is generated to unwanted pixels to display the peripheral pixels. do.

Therefore, in order to prevent this phenomenon, a certain voltage should not be applied to the non-selected pixel. In particular, in order to increase the contrast, the voltage ratio applied to the selected or non-selected pixels should be increased.

In particular, if the number of shots increases in the display device, the display amount increases, so the duty of the driving or waveform should be reduced. In this case, the luminance is further reduced.

On the other hand, when the dot matrix is enlarged in the static driving method, memoryization becomes an absolute requirement in terms of fluctuation. Therefore, the memory element must be wired in the matrix wiring. For example, in the pulse memory method, a resistor must be connected to each pixel, which has a disadvantage of complicating the entire circuit. The control circuit of the most representative multicolor LED dot matrix so far in this prior art is shown in FIG. As shown in the figure, the matrix is composed of a matrix in a row direction 16 and a column direction 16. The row direction is connected to the data circuit of the drive circuit and the column direction is connected to the prescan circuit.

The data circuit includes a first switch circuit 1 serving as a logic circuit, a shift register 2 and 3 of 16 stages x 16 blocks, and a current amplification control of the 16 stage output from the first block of the shift register. Amplification circuits 4. The pre-scan circuit comprises a second switch circuit 5, first and second FF counters 6 and 7, a decoder 8 and a current amplifier circuit 9 that amplifies the output of the decoder. However, in accordance with the reset signal, the first FF counter is set to an initial state, and a line is selected as a ship owner society which becomes an initial state. The image data is then written into the shift register corresponding to the clock signal.

In such a line scanning circuit, since the output of the first FF counter 6 is converted to the first clock signal and the first line is selected, image data is displayed on the first line from the first clock of the shift register. The second line is selected as the input of the seventeenth clock signal. From the 17th to the 32nd clock signal inputs, image data appears in the second line from the first clock of the shift register and the image data shown in the first line moves to the second block.

Therefore, when the sequential line scan is replaced, image data corresponding to the line is output from the first block. When the next line scan is continuously executed after the completion of scanning by writing one line, the image is shifted to the image data shift register and the image flows and cannot be seen as a picture.

However, after the one-line scan is completed, the pause period is set between the next line scan to maintain the line lighting. Therefore, in the case of data movement in the shift register, the LED lighting is shown as an image. However, the carrier signal is supplied from the first FF counter 6 to the decoder 8 via the second FF 6, and at the same time, the output of the pre-scan is stopped.

The luminance adjustment of the display section uses a luminance signal that can be arbitrarily width-modulated between 1-15 syringes in units of 16 clocks. When the carrier signal from the first FF counter 6 is at a low level, the operation state is turned on, and the lighting time of the LED is adjusted in response to the pulse width of the luminance signal.

Therefore, such a prior art cannot read data for display while moving data in a register, and on the contrary, it is impossible to input data while data is being displayed, so that the display time is reduced when the display contents change frequently. That is, the scanning time is shortened between line scans, resulting in a decrease in luminance and a screen shaking.

In addition, the technology distinguishes the input of image data, but according to the selection signal, each input data is sequentially input to the first line, sequentially displayed on the corresponding line, and the clock signal is turned on to turn on the LED. After the counter, the decoder selects one line and repeats the above steps in accordance with the duty cycle of the modulated luminance signal with the pulse width.

Therefore, the image data needs to be distinguished by this operation, and various screen configurations are difficult because the idle period in the duty cycle is required during the process of sequentially scanning each line.

SUMMARY OF THE INVENTION The present invention aims to provide a control circuit and a method of a dot matrix display device capable of arbitrarily adjusting a rest period in a duty cycle between data display in order to solve this disadvantage.

Another object of the present invention is to provide a control circuit and a control method capable of obtaining various software effects because the multicolor dot matrix display device is selectively operated to display a predetermined color, thereby diversifying the image configuration to be displayed.

To this end, the present invention, for example, the line selection signal is encoded in the decoder and then control the column of the dot matrix, and the data signal during the clock signal generation period, for example red data and green data are input to each shift circuit. At this time, the red and green data generated more than 16 clocks are transferred to the next module. Thus, the data latched by the latch signal by 16 bits per line is in response to an enable signal displaying and controlling red and green. Each line is output in parallel and then repeated 16 times in succession, thereby displaying an image.

As described above, the present invention allows the image display of the red and green data to be easily controlled in response to the two enable signals, and latches 16 lines of data in a row of dot matrices by the latch signal and temporarily suspends the enable signal. Since image display is performed by outputting in parallel to each other, the duty cycle between each line can be reduced, and the luminance of the image display can be improved by reducing the distance between the image consisting of all lines and the image.

In addition, the image software can be maximized to diversify the image on the display device according to two enable signals.

The present invention will be described in detail with reference to the accompanying drawings. As shown in FIG. 2, the input terminals include a clock signal terminal CLK, a latch signal terminal LAT, a red enable signal terminal R, a red data signal terminal RD, and a green data signal terminal GD. Address signal terminals A, B, C, and D for address selection of the green enable terminal G are provided.

Among these signals, the clock signal, the latch signal, the red enable signal, the red data signal, and the green enable signals are passed through the first buffer 21 and the line select signals are applied to the second buffer 22. The address signal in the case of the buffer 22 is applied to, for example, the 4 column 16 column decoder 23. The decoder 23 applies four input signals to sixteen selected low level signals to the dot matrix driving circuit 24. The dot matrix driving circuit 24 selects each column from the 16x16 dot matrix circuit 25 to drive control the LED.

On the other hand, the 16 x 16 dot matrix 25 of the red and green LEDs has two 8-bit registers 26 and 27 which are 16-bit registers for driving the red LED on one side thereof, and the registers 26 and 27. And a latch circuit comprising LED drivers 28 and 29 for driving control of the red LEDs in the column of the dot matrix circuit in accordance with the latch signal.

On the other side of the dot matrix circuit 25, a latch made up of two 8-bit registers 30 and 31 which are the same 16-bit registers as described above, and LED drivers 32 and 33 which drive-control the green LED. The circuit is connected.

On the other hand, a red data signal RD is connected to the 8-bit registers 26 and 27, and a green data signal GD is connected to the 8-bit registers 30 and 31.

When the clock signal is applied to the clock terminal SRCLK of each of the registers 36, 27, 30, and 31 in the case of the buffer 21, the clock signal has a rising edge. Each time, the red signal data RD is loaded on the input bus and input to the data terminals SER of the registers 26 and 27, and the green signal data is loaded on the input bus. The red and green signal data, which are serially inputted one bit data into the data terminal SER and generated 16 bits, that is, 16 clocks or more, are sequentially latched in such a manner as to be transferred to the next module.

Then, when the latched signal is applied to the terminal RCLK of each register at the time when the shifted red and green data is completed, the address signals A, B, C, and D are decoded by the decoder 23. Data of a specific line is latched among the 16 lines decoded.

At this time, if any one of the red and green enable signals R and G is at a low level and is applied to the terminals G of the registers 26 and 27 via the buffer 21, the LED driving circuit 28 (29), the red LED of the dot matrix circuit 25 is driven, and when applied to the terminal (G) of each register (30), (31), the dot by the LED driving circuit (32), (33) The green LED of the matrix circuit 25 is driven.

In the present invention, since the address signal is encoded by the decoder, the column of the matrix circuit is selected.

In the present invention, the red and green display data is shifted to each of the registers 26, 27, 30, and 31 according to the 16 clock signals, and the clock signal is shifted to the next module after 16 times. The data of a specific line is latched by the latch signal, and the driving of the red and green LEDs is repeated 16 times among the LEDs of the matrix columns already selected in the dot matrix circuit 25 according to the green and red enable signals. To display the image.

As described above, the present invention can provide a clear image by improving the luminance by reducing the duty cycle of the display signal.

Therefore, the present invention can be used in a wide range of fields, such as the display of the destination and departure time of the train or airplane at the station or aerodrome, etc., and the schedule indicator of the doctor or nurse in a hospital or the like.

Claims (2)

In the LED dot matrix control circuit, the clock signal terminal CLK, the latch signal terminal LAT, the red enable signal terminal R, the red data signal terminal RD, the green data signal terminal GD, the green enable Signal signals (G) and address signal terminals (A), (B), (C) and (D) for line selection, among the signals other than the red and green data signals (RD) (GD) are first The buffer 21 and the second buffer 22 are connected to the 4x16 column decoder 23 and the signals encoded by the 4x16 column decoder 23 are used to drive the dot matrix driving circuit 25. Two 8-bit registers connected to the red and green 16x16 dot matrix circuits 25, and 16-bit registers for driving the red and green LEDs in the red and green 16x16 dot matrix circuits 25. Each of (26), (27), (30), and (31) through LED drivers 28 and 29 for controlling red LED driving and LED drivers 32 and 33 for controlling green LED driving. A control circuit of an LED dot matrix, which is connected. In the LED dot matrix control method, the input clock signal CLK, latch signal LAT, red enable signal R, green enable signal G, address signals A, B, and ( C), (D) and decode them in the decoder 23 through the first buffer 21 and the second buffer 22 to select a column in a matrix circuit, and in the step of selecting a column in the matrix circuit. Shifting red and green display data according to 16 input clock signals; shifting to a next module when the clock signal is 16 or more times in the shifting step; and latching data of a specific line by a latch signal; Driving red and green LEDs in a row of columns of the selected matrix circuit to display in accordance with the input green and red enable signals, and displaying images by repeating the driving a predetermined time. LED dot matrix control method.

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