KR920007364B1 - Ic protected from heat - Google Patents

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Publication number
KR920007364B1
KR920007364B1 KR1019900002858A KR900002858A KR920007364B1 KR 920007364 B1 KR920007364 B1 KR 920007364B1 KR 1019900002858 A KR1019900002858 A KR 1019900002858A KR 900002858 A KR900002858 A KR 900002858A KR 920007364 B1 KR920007364 B1 KR 920007364B1
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temperature
temperature coefficient
circuit
positive
negative
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KR1019900002858A
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KR910017616A (en
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이형수
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금성일렉트론 주식회사
문정환
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The prevention circuit compensates the thermal shutdown temperature error caused by base to emitter voltage variation in manufacturing process. The circuit comprises a positive and a negative temperature coefficient bias circuit (11,13) having positive and negative temperature coefficient, and a comparator (12) for generating control signal when temperature rises upper limit by comparing the output voltage levels of the positive and negative temperature coefficient bias circuit (11,13).

Description

열파손 방지회로Thermal break prevention circuit

제1도는 종래 열파손 방지회로도.1 is a conventional thermal damage prevention circuit diagram.

제2도는 제1도에 따른 더멀셔트다운 특성도.FIG. 2 is a diagram illustrating the multiple shut down characteristic according to FIG. 1.

제3도는 본 발명 열파손 방지회로도.3 is a thermal damage prevention circuit diagram of the present invention.

제4도는 본 발명에 따른 더멀셔트타운 특성도.4 is a characteristic diagram of a mulberry town in accordance with the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 정특성온도계수바이어스회로 12 : 비교회로11: static temperature coefficient bias circuit 12: comparison circuit

13 : 부특성온도계수바이러스회로 Vo : 제어출력13: Negative temperature coefficient virus circuit Vo: Control output

본 발명은 열파손 방지회로(Thermal protection)에 관한 것으로, 특히 공정상 소자의 베이스-에미터간전압(VBE)의 변동에 의한 더멀셔트다운(Thermal Shutdown)온도변화를 방지하여 적절한 온도에서 동작하도록 하기 위한 열파손 방지회로에 관한 것이다.The present invention relates to a thermal protection circuit (thermal protection), in particular to prevent the thermal shutdown due to variations in the element-emitter voltage (V BE ) of the device in the process to operate at an appropriate temperature It relates to a thermal damage prevention circuit for.

종래 열파손 방지회로를 첨부된 도면을 참조해 설명하면 다음과 같다.The conventional thermal damage prevention circuit will be described with reference to the accompanying drawings.

제1도는 종래 열파손 방지회로도로서, 이에 도시된 바와같이 기준전압(Vref)을 에미터에 인가받고, 다중콜렉터중 하나를 그의 베이스에 접속한 다중콜렉터 피엔P 트랜지스터(Q1)와, 그 피엔피트랜지스터(Q1)의 다중콜렉터중 하나의 콜렉터와 접속된 콜렉터에서 출력(Vo)하도록 하고, 상기 피엔피트랜지스터(Q1)의 일측콜렉터에 베이스가 접속된 트랜지스터(Q2)와, 상기 피엔피트랜지스터(Q1)의 베이스와 바이어스조정저항(R1), (R2)을 통해 베이스가 접속되고, 그의 콜렉터가 상기 트랜지스터(Q2)의 베이스에 접속되어 그 트랜지스터(Q2)를 제어하는 트랜지스터(Q3)로 구성되었다.FIG. 1 is a conventional thermal damage prevention circuit diagram. As shown in FIG. 1, a multi-collector PEN P transistor Q1 having a reference voltage Vref applied to an emitter and connected one of the multi-collectors to its base, The output Vo is connected to a collector connected to one of the multiple collectors of the transistor Q1, and a base Q2 is connected to one collector of the PNP transistor Q1, and the PNP transistor Q1. A base is connected through a base of bias) and bias adjustment resistors R1 and R2, and a collector thereof is connected to the base of the transistor Q2 to constitute a transistor Q3 for controlling the transistor Q2.

이와같이 구성된 종래 열파손 방지회로의 작용 및 문제점을 설명하면 다음과 같다.Referring to the operation and problems of the conventional thermal damage prevention circuit configured as described above are as follows.

기준전압(Vref)에 대해 적당한 저항값을 갖는 저항(R1), (R2)을 선택하여 트랜지스터(Q3)의 베이스 전압이 특정온도 이하에서는 그 트랜지스터(Q3)를 턴온시키지 않도록 한다. 트랜지스터(Q1)의 베이스-에미터간 전압(VBE)은 온도의 함수로써 표현하면 다음과 같다.The resistors R1 and R2 having appropriate resistance values with respect to the reference voltage Vref are selected so that the transistor Q3 is not turned on when the base voltage of the transistor Q3 is below a specific temperature. The base-emitter voltage V BE of transistor Q1 is expressed as a function of temperature as follows.

VBE(T)=BE,STD+α.△T V BE (T) = BE, STD + α. △ T

여기서, VBE,STD는 특정전류에서 25℃온도에서의 VBE전압이고, α는 VBE의 온도계수로 약-2mV/℃의 부특성을 갖으며, △T는 온도상승분을 보인 것이다.Here, V BE, STD is the V BE voltage at 25 ℃ temperature at a particular current, α will have had the characteristic section of about -2mV / ℃ in temperature coefficient of V BE,T is the temperature rise shown.

제2도는 종래 열파손 방지회로에서 V2의 변화특성도로서, VBE는 트랜지스터(Q3)의 턴온전위이고, A점은 정상적인 셔트다운(Shutdown)이 일어나는 점이며, A점 좌측은 공정상 VBE변화에 의한 비정상적인 셔트다운이 일어나는 것을 보인 특성도이다.2 is a change characteristic diagram of V2 in the conventional thermal damage prevention circuit, where V BE is the turn-on potential of transistor Q3, point A is a normal shutdown, and point A is to the left of process A. This is a characteristic diagram showing abnormal shut down caused by BE change.

온도가 상승하면 트랜지스터(Q1)의 VBE전압이 작아져 그의 베이스전압(V1)이 상승하므로 트랜지스터(Q3)의 베이스전압(V2)이 올라가게 되고 마침내 특정온도인 더멀셔트다운 온도에서 트랜지스터(Q3)가 턴온되어 출력 상태가 바뀌게 된다.When the temperature rises, the V BE voltage of the transistor Q1 decreases and its base voltage V1 rises, so that the base voltage V2 of the transistor Q3 goes up, and finally the transistor Q3 at a specific temperature, which is a further shutdown temperature. ) Is turned on and the output state changes.

이와같이 종래 회로에서는 더멀셔트다운온도는 VBE턴온전압에 영향을 받는데, 이 VBE턴온전압은 공정상의 문제로 인해 약±0.05[V]의 오차가 생길 수 있어서, 더멀셔트다운 온도가 ±25℃정도의 오차가 발생되므로 오동작을 초래할 수 있다.Thus the conventional circuit, the deomeol shut-down temperature is influenced in V BE turn-on voltage, V BE turn-on voltage because of a problem in the process according may cause an error of approximately ± 0.05 [V], the deomeol shut down temperature ± 25 ℃ An error of degree may occur and cause a malfunction.

본 발명은 이와같은 종래 문제점을 해소시키기 위하여 공정상 VBE전압의 변동에 의한 더멀셔트다운 온도변화를 방지하며 적절한 온도에서 동작하도록 하기 위한 회로를 창안한 것으로, 이를 첨부한 도면을 참조해 설명하면 다음과 같다.The present invention has been devised a circuit for operating at an appropriate temperature to prevent the thermal shutdown temperature change caused by the variation of the V BE voltage in the process to solve such a conventional problem, will be described with reference to the accompanying drawings As follows.

제3도는 본 발명 열파손 방지회로도로서, 이에 도시한 바와같이 전류원 및 입력바이러스를 위한 트랜지스터(Q2), (Q3), (Q1)와 온도계수결정을 위한 트랜지스터(Q4), (Q5), 및 저항(R1∼R3)과 바렉터다이오드(D1), (D2)로 구성되어 일종의 밴드 겝(band gap)회로 작용을 하여 정특성온도계수를 나타내는 정특성온도계수바이어스회로(11)와, 상기 정특성온도계수바이어스회로(11)와 마찬가지로 트랜지스터(Q8), (Q9), (Q10), 트랜지스터(Q11), (Q12) 및 저항(R4∼R6)과 바렉터다이오드(D3), (D4)로 구성되어 부특성온도계수를 나타내도록 한 부특성온도계수바이어스회로(13)와, 상기 정특성 및 부특성온도계수바이어스회로(11), (13)의 출력전압(V1), (V2)을 비교하여 출력(Vo)하는 비교회로부(12)로 구성하였다.3 is a circuit break prevention circuit diagram of the present invention, in which the transistors Q2, Q3, Q1 for the current source and the input virus and the transistors Q4, Q5, for determining the temperature coefficient, and A static temperature coefficient bias circuit 11 composed of resistors R1 to R3, varactor diodes D1, and D2, which acts as a band gap circuit and exhibits a static temperature coefficient; Similar to the characteristic temperature coefficient bias circuit 11, the transistors Q8, Q9, Q10, transistors Q11, Q12, resistors R4 to R6, and varactor diodes D3 and D4 are used. The output voltages V1 and V2 of the negative characteristic temperature coefficient bias circuit 13 and the positive and negative characteristic temperature coefficient bias circuits 11 and 13, which are configured to exhibit the negative characteristic temperature coefficient, are compared. And a comparison circuit section 12 that outputs Vo.

이와같이 구성된 본 발명의 작용 및 효과를 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured as described above are as follows.

여기서, 스위치(SW1), (SW2)는 동작시작(Start)시만 온시켜주어 본 고안 회로가 동작되도록 한다.Here, the switches SW1 and SW2 are turned on only at the start of operation so that the inventive circuit is operated.

먼저, 정특성온도계수바이어스회로(11)의 온도계수결정은 다음 식(1∼3)에 의해 결정된다.First, the temperature coefficient determination of the static temperature coefficient bias circuit 11 is determined by the following equations (1 to 3).

Figure kpo00001
Figure kpo00001

Figure kpo00002
Figure kpo00002

Figure kpo00003
Figure kpo00003

또한, 부특성온도계수바이어스회로(13)의 온도계수결정은 다음 식(4∼6)에 의해 결정된다.The temperature coefficient of the negative temperature coefficient bias circuit 13 is determined by the following equations (4 to 6).

Figure kpo00004
Figure kpo00004

Figure kpo00005
Figure kpo00005

Figure kpo00006
Figure kpo00006

여기서, m, n은 트랜지스터(Q4), (Q12)의 베이스-에미터간 전압(VBE,Q4), (VBE,Q12)이다.Where m and n are base-emitter voltages V BE and Q4 and V BE and Q12 of transistors Q4 and Q12 .

이와같은 식(1∼6)에 의해 결정되는 온도계수에 따라 정특성온도계수바이어스회로(11)의 출력전압(V1)은 부특성온도계수바이어스회로(13)의 출력전압(V2)보다 낮게 설정한다. 이러한 조건에서 만약 온도가 올라가면 정특성온도계수바이어스회로(11)의 출력전압(V1)은 온도계수가 정특성이므로 상승하게 되고, 부특성온도계수바이어스회로(13)의 출력전압(V2)은 온도계수가 부특성이므로 하강하게 된다. 결국 특정온도이상에서는 출력(Vo)상태가 변하게 되는데, V1, V2전압이 윗 식(1), (4)에 의해 결정되므로 둘다 VBE전압강하에 의해 결정된다.The output voltage V1 of the static characteristic temperature coefficient bias circuit 11 is set lower than the output voltage V2 of the negative characteristic temperature coefficient bias circuit 13 according to the temperature coefficient determined by the above equations (1 to 6). do. Under these conditions, if the temperature rises, the output voltage V1 of the positive temperature coefficient bias circuit 11 rises because the temperature coefficient is positive, and the output voltage V2 of the negative temperature coefficient bias circuit 13 becomes a temperature coefficient. Since it is a negative characteristic, it falls. As a result, the output (Vo) state changes above a certain temperature. Since the voltages V1 and V2 are determined by the above equations (1) and (4), both are determined by the V BE voltage drop.

만약 공정상 요인으로 VBE가 변하게 되면 V1, V2 둘 다 같은 방향으로 변하게 되어 더멀셔트다운 동작온도가 변하지 않게 된다.If V BE is changed due to process factors, both V1 and V2 are changed in the same direction so that the operating temperature of the multiple shut down does not change.

즉, 제4도 본 발명 회로에 따른 특성도에 도시한 바와같이 (가)점의 정상셔트다운시점과, (나)점의 공정상 VBE오차로 인한 셔트다운시점이 같은 온도(To)에 위치하게 된다.That is, as shown in the characteristic diagram according to the circuit of the invention of FIG. 4, the normal shut-down time of point (A) and the shutdown point due to V BE error in the process of point (B) are at the same temperature (To). Will be located.

이상에서 설명한 바와같이 본 발명은 더멀셔트다운 온도의 오차가 거의 발생되지 않으므로 집적회로에서 회로보호 및 오동작을 유발하지 않는 효과가 있다.As described above, the present invention has an effect of not causing circuit protection and malfunction in the integrated circuit since the error of the thermal shutdown temperature is hardly generated.

Claims (1)

일정온도이상이 되면 집적회로를 보호하기 의해 제어신호가 발생되도록 한 열파손 방지회로에 있어서, 온도가 올라가면, 출력전압(V1), (V2)이 상승 및 하강하는 정특성 및 부특성온도계수에 따라 밴드 갭(band gap)작용의 정특성 및 부특성온도계수바이어스회로(11), (13)와, 상기 정특성 및 부특성온도계수바이어스회로(11), (13)의 출력전압(V1), (V2)을 비교하여 제어출력(Vo)을 하도록 하는 비교회로(12)로 구성한 것을 특징으로 하는 열파손 방지회로.In the thermal damage prevention circuit which generates a control signal by protecting the integrated circuit when the temperature is higher than a predetermined temperature, when the temperature rises, the output voltages V1 and V2 rise and fall to the positive and negative characteristic temperature coefficients. According to the band gap function, the positive and negative temperature coefficient bias circuits 11 and 13 and the output voltage V1 of the positive and negative temperature coefficient bias circuits 11 and 13 And a comparison circuit (12) which compares (V2) and makes a control output (Vo).
KR1019900002858A 1990-03-05 1990-03-05 Ic protected from heat KR920007364B1 (en)

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