KR920007156A - Resin Sealed Semiconductor Device - Google Patents

Resin Sealed Semiconductor Device Download PDF

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Publication number
KR920007156A
KR920007156A KR1019910015685A KR910015685A KR920007156A KR 920007156 A KR920007156 A KR 920007156A KR 1019910015685 A KR1019910015685 A KR 1019910015685A KR 910015685 A KR910015685 A KR 910015685A KR 920007156 A KR920007156 A KR 920007156A
Authority
KR
South Korea
Prior art keywords
semiconductor device
sealed semiconductor
resin sealed
island regions
resin
Prior art date
Application number
KR1019910015685A
Other languages
Korean (ko)
Other versions
KR950012920B1 (en
Inventor
시게키 사코
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920007156A publication Critical patent/KR920007156A/en
Application granted granted Critical
Publication of KR950012920B1 publication Critical patent/KR950012920B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

내용 없음.No content.

Description

수지밀봉 반도체장치Resin Sealed Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명의 제 1 실시예에 따른 수지밀봉 반도체장치를 나타낸 평면도,1 is a plan view showing a resin sealing semiconductor device according to a first embodiment of the present invention,

제 2 도는 상기 제 1 도의 X-X'선에 따른 단면도,2 is a cross-sectional view taken along line X-X 'of FIG. 1;

제 3 도는 본 발명의 제 2 실시예에 따른 수지밀봉 반도체장치를 나타낸 평면도,3 is a plan view showing a resin sealing semiconductor device according to a second embodiment of the present invention;

제 4 도는 상기 제 3 도의 X-X'선에 따른 단면도,4 is a cross-sectional view taken along line X-X 'of FIG. 3;

제 5 도 및 제 7 도는 각각 종래의 수지밀봉 반도체장치를 나타낸 평면도,5 and 7 are plan views each showing a conventional resin-sealed semiconductor device,

제 6 도는 상기 제 5 도의 X-X'선에 따른 단면도,6 is a cross-sectional view taken along line X-X 'of FIG. 5;

제 8 도는 상기 제 7 도의 X-X'선에 따른 단면도,8 is a cross-sectional view taken along line X-X 'of FIG. 7;

제 9 도는 종래의 수지밀봉 반도체장치에서 발생한 수지크랙을 나타낸 단면도,9 is a cross-sectional view showing a resin crack generated in a conventional resin-sealed semiconductor device;

제 10 도는 섬영역의 면적과 수지의 두께와의 관계를 나타낸 도면이다.10 is a diagram showing the relationship between the area of the island region and the thickness of the resin.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11-1,11-2 : 섬영역 12-1,12-2 : 반도체소자11-1,11-2: Island area 12-1,12-2: Semiconductor device

13 : 접착제(반도체소자용) 14 : 내부리드13: adhesive (for semiconductor device) 14: inner lead

15 : 본딩와이어 16 : 배선패턴15: bonding wire 16: wiring pattern

17 : 절연회로기판 18 : 접착제(절연회로기판용)17: insulated circuit board 18: adhesive (for insulated circuit board)

19 : 몰드수지19: Mold Resin

Claims (2)

반도체소자(12-1, 12-2)가 탑재되는 복수의 섬영역(11-1, 11-2)을 갖춘 리드프레임과, 상기 복수의 섬영역위에 걸치도록 하여 탑재되는 절연회로기판(17)을 포함하여 구성된 것을 특징으로 하는 수지밀봉반도체장치.A lead frame having a plurality of island regions 11-1 and 11-2 on which the semiconductor devices 12-1 and 12-2 are mounted, and an insulated circuit board 17 mounted over the plurality of island regions. Resin sealing semiconductor device, characterized in that configured to include. 반도체소자(12-1, 12-2)가 탑재됨과 더불어 서로 전기적으로 접속되는 복수의 섬영역(11-1, 11-2)을 갖춘 리드프레임과, 상기 복수의 섬영역위에 걸치도록 하여 탑재되는 절연회로판(17)을 포함하여 구성된 것을특징으로 하는 수지밀봉반도체장치.A lead frame having a plurality of island regions 11-1 and 11-2 which are mounted on the semiconductor elements 12-1 and 12-2 and electrically connected to each other, and which are mounted on the plurality of island regions. A resin sealing semiconductor device characterized by comprising an insulated circuit board (17). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910015685A 1990-09-11 1991-09-09 Plastic-molded type semicodnuctor device KR950012920B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-238883 1990-09-11
JP2238883A JP2928611B2 (en) 1990-09-11 1990-09-11 Resin encapsulated semiconductor device

Publications (2)

Publication Number Publication Date
KR920007156A true KR920007156A (en) 1992-04-28
KR950012920B1 KR950012920B1 (en) 1995-10-23

Family

ID=17036685

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015685A KR950012920B1 (en) 1990-09-11 1991-09-09 Plastic-molded type semicodnuctor device

Country Status (2)

Country Link
JP (1) JP2928611B2 (en)
KR (1) KR950012920B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117100A (en) 1997-06-19 1999-01-22 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
KR950012920B1 (en) 1995-10-23
JPH04119640A (en) 1992-04-21
JP2928611B2 (en) 1999-08-03

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