KR920006853B1 - Thin junction manufacturing method of cmosfet with stacked capacitor - Google Patents

Abstract

The method for forming a shallow junction of the source and drain of a CMOSFET connected to a stacked capacitor comprises: forming a gate electrode (6) on a P-substrate (1) having an N-well (3), a P- well (2), an insulation oxide film (4) and a gate oxide film (5); forming a charge storage electrode (9) thereon, forming a drain region (13') of a cell moving gate thereon to forming a stacked capacitor; forming source and drain regions (18,18') of a CMOSFET adjacent to the cell moving gate; thereby forming a shallow junction with a junction depth of less than 0.1 μs to improve the density of the semiconductor IC.

Description

Shallow junction manufacturing method of source and drain of CMOSFET with stacked capacitor structure

1A to 1E are cross-sectional views showing a step of forming a CMOSFET to which a stacked capacitor structure according to the prior art is connected.

2A to 2E are sectional views showing a step of forming a CMOSFET to which a stacked capacitor according to the present invention is connected.

* Explanation of symbols for main parts of the drawings

1: P-type substrate 2: P-Well

3: N-well 4: insulation oxide film

5: gate oxide film 6: conductive material for gate electrode

7: LDD (Lightly Doped Drain) Area

8 and 22: oxide layer 9: conductive material for charge storage electrode

10: capacitor oxide film layer (ONO layer)

11: conductive material for VCC / 2 electrode

13 and 13 ': N + type source region and drain region

12, 15, 17, 20, 21: photosensitive material

14 and 19: spacer oxide film

16 and 16 ': N + type source region and drain region

18 and 18 ': P + type source region and drain region

23 and 23 ': diffused N + source and drain regions

24 and 24 ': diffused P + source and drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a source and drain shallow junction of a CMOSFET connected with a stacked capacitor structure in a highly integrated semiconductor device, and more particularly, in a high temperature process of forming a stacked structure capacitor having a junction area of a source and drain region. The present invention relates to a method of manufacturing a source and drain shallow junction of a CMOSFET to which a stacked capacitor structure is connected, which can prevent the formation thereof and to form a junction area appropriately to improve the characteristics of a semiconductor device.

In the conventional method of forming a source and drain region of a CMOSFET for a storage device of a stacked capacitor structure, an N-type or P-type source and drain region is formed after a gate electrode is formed, and then a capacitor region of a stacked structure is formed. Since the junction depth of the source and drain regions of the CMOSFET is a high temperature process during the formation of a capacitor having a stacked structure (i.e., a high temperature process and a capacitor corresponding to the deposition and doping process of polysilicon for charge storage electrodes of a multilayer capacitor) In order to improve the insulation characteristics when forming a dielectric film, when forming a composite dielectric material of Oxide-Nitrie-Oxide (ONO) structure, the high temperature process during the first oxide film growth process, the high temperature process when the nitride film is deposited, the high temperature process when the oxide film is grown, and the capacitor High temperature process corresponding to deposition and doping process of polysilicon for plate electrode) It is formed deeper than the added high temperature process. Therefore, due to the increase in the junction depth of the source and drain regions, the effective channel length for the moving gate in the operating region and the effective channel length for the separation region between the operating regions are reduced. Therefore, this problem causes a problem for high integration of the semiconductor device.

In order to solve the above problems with the conventional manufacturing method, the drain of the cell transfer gate when forming the stacked capacitor charge storage electrode is formed without forming the source and drain regions of the CMOSFET immediately after the gate electrode is formed as in the conventional method. A method of manufacturing a method of forming a shallow junction of a source and a drain region of a CMOSFET to which a stacked capacitor structure is connected by forming a source and a drain region of a peripheral CMOSFET of a cell moving gate by forming an area and then forming a stacked capacitor and then performing an ion implantation process. The purpose is to provide.

According to one aspect of the present invention, in order to obtain a shallow junction depth of a source / drain region of a CMOSFET used for a memory device and a peripheral circuit having a stacked capacitor cell structure of a semiconductor highly integrated memory device, N− is applied to the P-type substrate 1. Forming the well 3 and the P-well 2, and then forming an insulating oxide film 4 in a predetermined region by a LOCOS process, and implanting ions into the entire region exposed to the P-type impurities for controlling the threshold voltage. Then, the gate oxide film 5 is grown on the N-well 3 and the P-well 2, and polysilicon is deposited thereon, and the gate electrodes 6 are formed in predetermined regions, respectively. And forming a predetermined LDD region 7 in the N-wells 3 and P-wells 2 at the lower left and right sides of the gate electrode, and on the N-wells 3 and P-wells 2. Forming an oxide layer 8 on the formed gate electrode 6, the LDD region 7 and the insulating oxide film 4, and a predetermined portion of the upper portion of the P-well 2. For charge preservation electrodes, such as polysilicon, on top of the oxide layer 8 to remove the gate oxide layer 5 and the oxide layer 8 of the layer 25 and to form an N + drain region under the removed portion 23. Depositing a conductive material 9 and connecting the LDD region 7 to ion implantation of arsenic (As) or phosphorus (P) with an N-type impurity; Etching all but leaving a predetermined portion, forming an ONO layer on the conductive material 9 for the charge storage electrode, and a VCC / 2 electrode conductive material on the ONO layer 10 and the oxide layer 8. (11) depositing with polysilicon or the like to form the upper photosensitive material 12, and removing the photosensitive material 12 only to be part of the stacked capacitor region, and then removing the conductive material for the VCC / 2 electrode (11). ) And the oxide layer 8 exposed by anisotropic etching is etched to form the spacer oxide layer 14. In the step of forming a stacked capacitor, an N + type impurity implanted into the LDD region 7 and the P well 2 region from the conductive material 9 for the charge storage electrode is diffused to form an N + type drain region ( 13 ') is formed, the photosensitive material 12 is removed on the P-well 2, and then the photosensitive material 15 is formed on the N-well 3, followed by N such as arsenic (As). Ion implantation into the P-well (2) region to form a doped VCC / 2 electrode conductive material (11) and an N + type source region (13) in the P-well (2); And removing the photosensitive material 15 on the N-well 3, and then forming the photosensitive material 17 on the P-well 2, and impurities such as boron in the N-well 3. Ion implantation to form P + source and drain regions 18 and 18 '.

In the above-described invention, since the CMOSFET source and drain regions are formed after the stacked capacitor fabrication process, the junction depth can be formed at least shallower than at least 0.1 [mu] m, compared with the conventional method, thereby achieving high semiconductor integration.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

1A to 1E are cross-sectional views illustrating a method of forming a source and drain region of a CMOSFET to which a stacked capacitor structure according to the prior art is connected. It is shown.

1A is a diagram illustrating a manufacturing process of a memory device having a stacked capacitor structure according to the related art.

The N-well 3 and the P-well 2 are formed on the P-type substrate 1 in the same manner as in a general CMOS process, and then an insulating oxide film 4 is formed on a predetermined portion by a local oxidation of silicon (LOCOS) process. To form. Subsequently, in order to control the threshold voltage of the N-MOSFET and the P-MOSFET, P-type impurities are implanted into the entire exposed region, the gate oxide film 5 is grown, and a material of polysilicon is deposited to deposit N. The gate electrode 6 is formed on the well 3, the P well and the insulating oxide film 4. In addition, in order to improve the hot carrier effect generated in the short channel device, the LDD (Lightly Doped Drain) 7 is formed by ion implantation at the lower left and right sides of each gate electrode 6 after the formation of the gate electrode 6. ) It is sectional drawing of the state formed.

In FIG. 1B, an oxide film is formed to a predetermined thickness over the entire P-well 2 and N-well 3 regions, and then spacer oxide films 19 are formed on sidewalls of the gate electrodes 6 by anisotropic etching. After that, the photosensitive material 20 is formed on the N-well 3, and the N + source and drain regions 16 and 16 'are formed by ion implantation of high concentration N-type impurities.

Figure 1c shows that after removing the photosensitive material 20 on the N-well 3 after the process, the photosensitive material 21 formed on the P-well 2 is formed, and then the P-type high concentration impurity is formed in the N-well. Fig. 3 is a cross sectional view showing the P + type source and drain regions 18 and 18 'formed at the lower left and right sides of the gate electrode 6 by ion implantation into the region.

FIG. 1D is a cross-sectional view of the oxide film 22 formed as a whole on the P-well 2 and the N-well 3 after the above process.

FIG. 1E shows the gate oxide film 5 and the portion 25 of the oxide film layer 22 over the N + -type drain region 16 'in the P-well 2 region removed to connect the stacked capacitor after the process. Thereafter, the conductive material 9 for the charge storage electrode is deposited at 500-700 ° C. for several minutes to several minutes. Thereafter, the conductive material 9 for charge preservation electrode is doped with impurities for several minutes to several hundred minutes at 700-950 ° C., and only a portion is left as shown in the drawing, and all others are removed. Next, an oxide film is formed for several minutes to several minutes at 700-1000 ° C., for example, to form an ONO layer (Oxide-Nitride-Oxide) 10 as a capacitor dielectric film on the conductive material 9 for the charge storage electrode. After forming the nitride film and the oxide film, only a predetermined portion is left as shown in the drawing, and all others are removed. Thereafter, the conductive material 11 for the VCC / 2 electrode is formed at a predetermined thickness of moisture-decade for several minutes at 500-700 ° C, and then doped with impurities for several minutes to several hundred minutes at 700-950 ° C, leaving only a predetermined portion as shown in the drawing. It is sectional drawing of the state removed.

As described above, the conventional technology allows the N + type source and drain regions 16 and 16 'and the P + type source and drain regions 18 and 18' to be subjected to a high temperature process for a long time at a high temperature to form a stacked capacitor. Then, the N + type source and drain regions 16 and 16 'are further diffused into the underlying silicon to form diffused source and drain regions 23 and 23', and the P + type source and drain regions 18 and 18 'are formed. As the diffused and diffused P + source and drain regions 24 and 24 'are formed, problems such as the effective channel depth and the effective channel length for the separation region between the operating regions are reduced.

Accordingly, FIGS. 2A through 2E are detailed descriptions of the process steps of the present invention for solving the problems of the prior art.

FIG. 2A is the same as that of FIG. 1A of the conventional process step to form the N-well 3, the P-well 2 and the insulating oxide film 4 on the P-substrate 1, and then the gate oxide film 5 ) And the respective gate electrodes, a detailed description thereof will be omitted in order to avoid repeated description and briefly describe the specification.

FIG. 2B is a cross-sectional view of the LTO (Low Temperature Oxide) oxide film layer 8 formed entirely on the N-well 3 and the P-well 2 after the above process.

FIG. 2C illustrates a portion of the gate oxide film 5 and the oxide film layer 8 on the LDD region 7 in order to connect the stacked capacitor after the process to the LDD region 7 formed in the P-well 2. After removing 25), polysilicon for the conductive material for charge storage electrode is deposited on the oxide layer 8 at a temperature of 500-700 ° C. for about several tens of minutes.

Then, impurity arsenic (As) or phosphorus (P) is ion-implanted into the polysilicon at a temperature of 700-950 ° C. for several minutes to several minutes, and then only a predetermined portion is left as shown in the drawing. Form and remove everything else. Thereafter, the ONO layer 10 for the capacitor dielectric film is formed in the same manner as the conventional method, and the VCC / 2 electrode is deposited on the ONO layer 10 by depositing a conductive material 11 for the VCC / 2 electrode with polysilicon or the like. The photosensitive material 12 is entirely formed on the conductive material 11.

Subsequently, as shown in the drawing, the photosensitive material 12 is removed while leaving only a predetermined portion, and then the conductive material 11 for the VCC / 2 electrode exposed to the bottom is etched, and the oxide layer 8 is subsequently anisotropically etched. ) Is a cross-sectional view of the spacer oxide film 14 formed on the left and right sides of the gate electrode 6 on the N-well 3 and the left side of the gate electrode 6 on the P-well 2, respectively. In the high temperature process of forming the stacked capacitor, N + type impurities implanted into the LDD region 7 and the P-well 2 region from the conductive material 9 for the charge storage electrode are diffused to form the N + type drain region 13 '. Is formed.

FIG. 2d removes the photosensitive material (12 in FIG. 2c) remaining on the P-well 2 and then forms the photosensitive material 15 on the N-well 3. Next, an N-type impurity such as arsenic (As) or phosphorus (P) is ion-implanted on the P-well 2 to form an N + -type source region 13 in the P-well 2 region and at the same time VCC It is sectional drawing in which the said impurity was doped in the electroconductive material 11 for / 2 electrodes.

FIG. 2E removes the photosensitive material (15 of FIG. 2D) remaining on the N-well 3 after the process and forms the photosensitive material 17 on the P-well 2. Then, P-type impurities such as boron (B) are ion-implanted into the N-well 3 to form P + source and drain regions 18 and 18 'at the lower left and right sides of the gate electrode 6. It is a cross section.

As described above, in the formation of the N-type MOSFET, the conventional technology proceeds to the formation of the capacitor of the gate electrode formation-spacer formation-source and drain region formation-laminated structure, but the present invention is a gate electrode formation-laminated structure. The process of capacitor formation and spacer formation-source and drain region formation of the process proceed. Therefore, in the present invention, the N + type impurities are diffused into the P-Well from the conductive material for the charge storage electrode in the high temperature process of forming the stacked capacitor to form the N + type drain region, and then the P + type source in the N + type source region and the N-well. By forming the region and the drain region, the effective channel length of the operation region can be properly maintained to improve the characteristics of the semiconductor device. In the present invention, when the conductive material for the VCC / 2 electrode is formed, the spacers can be formed at the same time, thereby simplifying the semiconductor manufacturing process.

Claims (1)

In order to obtain a shallow junction depth of a source / drain region of a CMOSFET used for a memory device having a stacked capacitor cell structure of a semiconductor highly integrated memory device and a peripheral circuit, an N-well 3 and a P-well on a P-type substrate 1 (2) and then forming an insulating oxide film 4 in a predetermined region by a LOCOS process, implanting P-type impurities for controlling the threshold voltage in all exposed regions, and then N-type (3 ) And growing the gate oxide film 5 on the P-well 2 and depositing polysilicon or the like on the P-well 2, and then forming gate electrodes 6 in predetermined regions, respectively, and N on the lower left and right sides of the gate electrode. Forming a predetermined LDD region (7) in the well (3) and the P-well (2), the gate electrode (6) formed on the N-well (3) and the P-well (2), LDD Forming an oxide layer 8 over the region 7 and the insulating oxide film 4, and for the gate oxide film 5 and the oxidation of the predetermined portion 25 over the P-well 2; In order to remove the film layer 8 and form an N + drain region under the removed portion 23, a conductive material 9 for charge storage electrode such as polysilicon is deposited on the oxide layer 8 to form an LDD region ( 7), ion implantation of arsenic (As) or phosphorus (P) with N-type impurities, etching all of the conductive material 9 for the charge storage electrode, leaving a predetermined portion, and Forming an ONO layer 10 on the conductive material 9 for the storage electrode, and converting the VCC / 2 electrode conductive material 11 on the ONO layer 10 and the oxide layer 8 to polysilicon or the like. Depositing and forming the upper photosensitive material 12, and removing and leaving only the portion of the photosensitive material 12 that will be the stacked capacitor region, and then etching the exposed conductive material 11 for the VCC / 2 electrode by anisotropic etching. Etching the exposed oxide layer 8 to form a spacer oxide layer 14; N + impurity implanted into the LDD region 7 and the P well 2 region from the conductive material 9 for the charge storage electrode during the high temperature process of forming a capacitor to form an N + drain region 13 ' Then, after removing the photosensitive material 12 on the P-well 2, and forming the photosensitive material 15 on the N-well (3), N-type impurities such as arsenic (As), etc. (2) ion implantation into a region to form a conductive material 11 for the doped VCC / 2 electrode and an N + type source region 13 in the P-well 2, and the N-well ( 3) removing the photosensitive material 15 thereon, and then forming a photosensitive material 17 on the P-well 2, and ion implanting P-type impurities such as boron into the N-well 3; Forming a P + type source region and a drain region (18 and 18 '), wherein the stacked capacitor structure is a shallow junction manufacturing method of a CMOSFET source and drain.

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