KR920006847B1 - Write unsafe check circuit of hard disk driver - Google Patents

Abstract

The circuit for checking the write unsafe signal generated by the hard disk controller controlling the write/read operation comprises: a delay part (41) delaying and reverse outputting the read/write signal outputted from the controller, an EXOR (43) outputting the reset pulse signal by exclusive logical summing of the read/write signal and delay output of delay part, a means for detecting the write unsafe signal by comparing the read/write signal with the write unsafe signal outputted from the preamp, a counter (50) generating the write unsafe disable signal by counting the clock and outputting the signal initialized by reset pulse of EXOR (43), a NAND gate (49) transforming the system clock into the counter clock.

Description

Hard drive write unsafe check circuit

1 is a conventional circuit diagram.

2 is a light unsafe signal waveform.

3 is an operating waveform diagram of FIG.

4 is a write unsafe check circuit according to the present invention.

5A and 5B are explanatory diagrams of FIG.

* Explanation of symbols for main parts of the drawings

41: delay circuit 42, 43: exclusive logic gate

45: inverter 47: divider

49, 55: NAND gate 53: counter

51: Andgate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard disk drive circuit, and more particularly to a circuit for accurately writing a write unsafe signal generated by a control of a hard disk controller that controls a write / read operation.

In general, a hard disk writes data to the hard disk or reads the recorded information under the control of a hard disk controller. During a recording operation, the hard disk is connected to a second degree from a pre-amp connected to the head HEAD. It is designed to detect the Write Unsafe (WUS) signal.

)신호를 출력하여 라이트(Write)동작을 수행시 발생된다.The write unsafe signal WUS is output from a preamplifier connected to the head.

This signal is generated when a write operation is performed by outputting a signal.

When the controller operates the light, the preamplifier checks the head drive current and the head wire state, and outputs a light unsafe signal that there is no problem when there is no error.When the head drive current is insufficient or the head wire is opened, the active amplifier writes the light. Outputs an unsafe signal.

At this time, the CPU for controlling the system inputs the write unsafe signal (WUS) output state output from the preamplifier and records the recording information (Data) on the hard disk through the preamplifier and the head when it is normal.

)를 출력하여 하드디스크를 제어하는 제어기(10)와, 상기 제어기(10)로부터 라이트 신호가 출력시 자기 채크하여 라이트 언세이프 신호(WUS)를 발생하고, 입력데이타에 의해 전류증폭하여 출력하는 프리앰프(12)와, 상기 프리앰프(12)와 제어기(10)로부터 각각 출력되는 라이트 언세이프 신호(WUS)와 라이트 신호(Write)를 배타적 논리합하여 비교출력하는 배타적 논리합 게이트(이하 EXOR이라 함)(14)과, 상기 EXOR(14)의 출력단자에 접속된 저항(R1)과 캐패시터(C1)로 구성된다. 이때 상기 프리앰프(12)에는 헤드(HEAD)(16)가 접속되어 상기 프리앰프(12)의 출력을 디스크(18)에 기록하거나, 디스크(18)가 픽업(pick-up)입력시 이를 전치 증폭출력한다.FIG. 1 is a conventional circuit diagram for checking the write unsafe signal as described above.

A controller 10 for controlling the hard disk by outputting a), and a pre-signal that generates a write unsafe signal (WUS) by self-checking when the write signal is output from the controller 10, and amplifies and outputs the current by the input data. Exclusive-OR gates (hereinafter, referred to as EXOR) that compare and output the exclusive operation of the write unsafe signal WUS and the write signal Write output from the amplifier 12, the preamplifier 12, and the controller 10, respectively. (14), a resistor (R1) and a capacitor (C1) connected to the output terminal of the EXOR (14). At this time, a head (HEAD) 16 is connected to the preamplifier 12 to record the output of the preamplifier 12 to the disc 18, or transpose it when the disc 18 is pick-up input. Amplify output.

2 is a waveform diagram for explaining the present invention.

When the controller outputs the write signal and writes the information to the DISK, the controller searches for the preamplifier head current and the headwire state connected to the head and writes the light unsafe when the write operation is not performed normally. Generate a signal.

)신호에 따른 라이트 언세이프(WUS)신호의 반응은 상기 제2도와 같다.Therefore, the central processing unit that checks the state of the write unsafe (WUS) signal during operation should check the status of the controller.

The response of the write unsafe (WUS) signal according to the?

The preamplifier self-checks the head drive current and the headwire state and outputs a low write unsafe signal (WUS) in response to a "low" write signal (active LOW) when normal, and the head drive current is insufficient. If the headwire is open, it generates an active " high " write safe signal WUS that indicates that recording is not possible.

3 is an operating waveform diagram of FIG.

)가 출력되어 EXOR(14)에 입력되면, 프리앰프(12)로부터는 헤드구동전류상태 및 헤드와이어 상태를 체크하여 라이트 언세이프신호(WUS)를 출력하여 EXOR(14)에 입력시킨다.The conventional circuit operation of FIG. 1 will be described with reference to FIG. 2 and FIG. Now from the controller 10 a write signal such as

Is output and input to the EXOR 14, the preamplifier 12 checks the head driving current state and the head wire state, and outputs the write unsafe signal WUS to the EXOR 14 for output.

If the write function can be normally performed, the write unsafe signal WUS as shown in FIG. 3b is output to the EXOR 14, and if the write function cannot be performed, the active "high" is output as the write unsafe signal WUS. .

At this time, when the normal write unsafe (WUS) signal is output from the preamplifier 12 as shown in FIG. 3b, the EXOR 14 outputs a comparison result between the two inputs. A pulse equal to 3c degrees is output.

)가 "하이"로 될때 약 1μsec의 시간을 가지고 트랜지션되기 때문이다. 이때 상기 EXOR(14)로부터 출력되는 펄스는 저항(R1) 캐패시터(C1)의 저역필터에 의해 필터링되어 차단되어 기록가능신호(

: Write OK)로 출력된다.The reason why the pulse is output as described above is that when the write signal is " low ", the write unsafe signal WUS is transitioned with a time of about 0.2 mu sec as shown in FIG.

This is because the transition of the transistors has a time of about 1 μsec when " high ". At this time, the pulse output from the EXOR 14 is filtered and blocked by the low pass filter of the resistor R1 capacitor C1 to record the signal (

: Write OK).

If there is an active "high" write unsafe (WUS) output from the preamplifier 12 due to lack of head drive current or open headwire, the EXOR 14 outputs and writes a logic "high" during the write period. It will output a signal indicating that it is disabled. However, since the conventional circuit operated as shown in FIG. 1 blocks the pulses generated by the EXOR 14 during the transition period of the write unsafe (WUS) signal by simply using a resistor and a capacitor, There was a problem that the circuit could malfunction due to an error or change, and the writing operation would not be executed correctly.

Accordingly, an object of the present invention is to accurately disable the write unsafe signal by disabling the transition period of the write unsafe signal generated from the preamplifier connected to the head when performing a write operation for recording data on the disk surface in the hard disk driver. It is to provide a circuit that can be detected.

Another object of the present invention is to provide a circuit for detecting a transition period of a write unsafe signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

)를 소정지연하고 반전출력하는 지연기(41)와, 상기 리이드/라이트 신호(

)와 지연기(41)의 지연출력 배타적 논리합하여 상호불일치 구간을 검출하여 출력하는 EXOR(43)와, 상기 지연기(41)의 지연출력과 프리앰프의 출력에 접속되어 지연된 리이드/라이트 신호(

)와 상기 프리앰프로부터 출력되는 라이트 언세이프 신호(WUS)를 비교하여 상기 불일치 구간을 비교검출하고 이를 반전 게이팅 출력하는 라이트 언세이프 신호 검출수단과, 상기 EXOR(43)의 출력신호 시스템 리세트 펄스에 의해 초기화되며, 소정의 클럭을 카운팅하여 라이트 언세이프 디스에이블 신호를 발생하는 카운터(53)와, 상기 카운터(53)의 출력단자와 시스템 클럭단자에 접속되어 상기 카운터(53)로부터 초기화 신호를 출력시 상기 시스템 클럭을 상기 카운터(53)의 클럭으로 제공하는 낸드게이트(49)와, 상기 카운터(53)와 라이트 언세이프 검출수단의 출력을 부논리곱하여 출력하는 라이트 언세이프 신호출력 게이트(이하 게이트라함)(55)로 구성된다.4 is a circuit diagram according to the present invention.

Delay delay (41) for predetermined delay and inverted output, and the lead / write signal (

) And an EXOR 43 for detecting and outputting a mutually inconsistent section by exclusive OR of the delay outputs of the delay unit 41, and a read / write signal delayed by being connected to the delay output of the delay unit 41 and the output of the preamplifier.

And the write unsafe signal detecting means for comparing and detecting the inconsistency interval by comparing the write unsafe signal WUS outputted from the preamplifier with the inverse gating output, and the output signal system reset pulse of the EXOR 43. The counter 53 is initialized and connected to a counter 53 for counting a predetermined clock and generating a write disable disable signal, and connected to an output terminal of the counter 53 and a system clock terminal. The NAND gate 49 which provides the system clock as the clock of the counter 53 at the time of output, and the write unsafe signal output gate which outputs the output of the counter 53 and the write unsafe detection means by a negative logic. Gate 55).

In the above configuration, reference numeral 47 denotes a divider for dividing the system clock (Clock: 4 MHz) by a D-flip flop, and 49 denotes the two divided signals and an output of the counter 53 by the AND gate. Logically multiply and provide a clock signal to the counter 53.

The write safe signal detecting means includes an EXOR 42 and an inverter 45 connected to the EXOR 42. The counter 53 is an asynchronous counter configuration in which the D-flip flops DF1, DF2, DF3, and DF4 are connected in series.

FIG. 5A and FIG. 5B are operation waveform diagrams of FIG. 4, and FIG. 5A is an operation waveform diagram when the write unsafe signal WUS in the normal recording state can be output from the pre-amp PRE-AMP. Fig. 8 is a waveform diagram of the operation when the write unsafe signal WUS is output in a state in which recording is impossible.

)나 라이트 언세이프 신호가 제4도의 회로에 입력된다. 가정하여 설명한다.In the following description with reference to FIGS. 5A and 5B attached to an operation example according to the present invention, the controller 10 and the preamplifier 12 of FIG. signal(

) And the write unsafe signal are input to the circuit of FIG. It is assumed and explained.

)가 제5a도 A와 같이 입력되면, 이는 홀수개의 인버터로 구성된 지연기(41)에 의해 제5a도 C와 같이 DT만큼 지연된 후 반전출력된다.The lead / light signal output from the controller to the circuit of FIG.

When 5a is inputted as shown in FIG. 5A, it is delayed by DT as shown in FIG. 5a as shown in FIG.

)와 상기 지연기(41)에서 DT만큼 지연된 리이드/라이트 신호(

)을 배타적 논리합하여 상호 불일치하는 구간펄스를 제5a도 E와 같이 출력한다.At this time, the EXOR 43 is a lead / light signal (

) And a lead / write signal delayed by DT in the delay unit 41

) Is exclusively ORed to output interval pulses inconsistent with each other as shown in FIG. 5A.

The " low " signal output from the EXOR 43 resets the counter 53, and when the output of the EXOR 43 becomes " high ", the counter 53 is divided into a 2 MHz divided system clock (1). / clock) prints an octal count.

The counter 53 is reset by the output of the EXOR 43 to output the initial " low " signal of the flip-flop DF4 as shown in FIG. 5A G, and a divided system clock of 1 MHz (1 / clock). The state is maintained until eight are input. When 4 MHz system clock is divided into 2 MHz clock by the divider 47 and eight pulses are continuously input to the clock terminal of the flip-flop DF1 through the NAND gate 49, The counter 53 outputs "high" as shown in FIG. 5A.

)가 천이시마다 4μsec의 "로우"신호를 낸드게이트(55)로 출력한다.That is, the counter 53 outputs a logic " high " when 4 mu sec (2 MHz X8) elapses after the reset by the output of the EXOR 43. Therefore, the counter 53 is a lead / light signal (

) Outputs a 4 μsec " low " signal to the NAND gate 55 at each transition.

In this state, when the write unsafe signal WUS such as B in FIG. 5A is input, the EXOR 42 exclusively ORs the outputs of the delay outputs 5a C and 5A B of the delay unit 41 to " The signal transitioned from "high" to "low" is detected and 5a is output as shown in D. FIG. At this time, the output of the EXOR 42 is inverted as shown in FIG. 5A by the inverter 45 and input to the NAND gate 55.

) 를 출력한다{펄스신호 (

) 가 "로우"이면 기록할 수 있음을 나타낸다}.Therefore, the NAND gate 55 negatively multiplies the outputs of the inverter 45, the EXOR 43, and the counter 53 by a pulse signal indicating that data can be written to a disc by a central processing unit (not shown).

Outputs {pulse signal (

) Is " low " to indicate that recording is possible.

)가 트랜지션(TRANSITION)된 후로부터 약 4μsec동안 "로우"상태를 유지함으로 라이트 언세이프 신호(WUS)가 트랜지션되는 동안(제2도 참조; B, D구간) 발생할 수 있는 오동작을 방지할 수 있게 된다.The signal output from the counter 53 is a write disable signal and a read / write signal (

) Stays "low" for about 4 μsec after the transition is performed to prevent malfunctions that may occur while the write unsafe signal WUS is transitioned (see Figure 2; sections B and D). do.

As described above, the present invention prevents write unsafe check errors that may occur during the transition period of the write unsafe signal generated from the preamplifier during the write operation in the hard disk driver by using a counter and a simple gate configuration. You can do exactly that.

Claims (1)

A controller for controlling the read / write of the hard disk by outputting a read / write signal (R / W), and the write unsafe signal (WUS) by checking the head driving current and the head wire open state when the write control signal is output from the controller. In a hard disk having a preamplifier for outputting and a write unsafe check circuit, a read / write signal output from a controller

Delay delay (41) for predetermined delay and inverted output, and the lead / write signal (

Is connected to the delay output of the delay unit 41 and the output of the preamplifier. Delayed lead / light signal (

) Is compared with the write unsafe signal (WUS) outputted from the preamplifier, and compares and detects the inconsistency interval, and inverts and outputs the inverse gating output, and is initialized by the reset pulse of the EXOR 43. And a counter 53 for outputting an initialization signal and counting a predetermined clock to generate a write disable disable signal, and an output terminal of the counter 53 and a system clock terminal for initialization from the counter 53. A NAND gate 49 which provides the system clock as a clock of the counter 53 when outputting a signal, and a write unsafe signal output gate which outputs the output of the counter 53 and the write unsafe detection means by negative logic. Circuit comprising: 55;

Images