KR920005605B1 - Led driving method - Google Patents

Abstract

The LED drive method uses a latch (14) instead of I/O ports of a MPU to output a driving current and a sync. current, thereby driving a number of LED's. The latch circuit includes data input ports (DI1-DI18) connected to display data output ports (D0-D3) and sync. data output ports (D4-D7) of the MPU (12), and output terminals (Q1-Q8) connected to row lines (RL1-RL4) and column lines (CL1-CL4) of a LED array (24). The latch circuit latchs the input display data and sync. data by a latch signal output of the MPU (12) to delay and output the source current and sync. current signal to the lines (RL1-RL4, CL1-CL4) of the LED array (24).

Description

LED drive method

1 is a conventional LED driver circuit.

2 is an LED driver circuit according to the present invention.

3 is an operational waveform diagram illustrating the operation of FIG.

* Explanation of symbols for main parts of the drawings

12 microprocessor 14 latch circuit

16-22: Resistance 24: Light Emitting Diode Array

LED1-LED16: Light Emitting Diode

The present invention relates to a LED drive method for driving a plurality of LEDs, and more particularly to a method for driving a plurality of LEDs installed in an electronic, communication system using a microprocessor.

Typically, an electronic communication system performing a predetermined function has at least one LED for displaying an operation state for displaying a current system operation state.

In particular, a system capable of performing a plurality of keys or a plurality of functions, for example, a keyphone telephone such as a keyphone system having a plurality of extension subscribers, etc., may have a current in-use state or a trunk line incoming state of each extension. It also has a lot of LEDs to indicate the status of Busy Busy status lights.

Currently in such a system, the circuit for driving a plurality of LEDs is as shown in FIG.

1 is a conventional LED driver circuit diagram, which includes a microprocessor having a predetermined number of display data output ports for displaying a state according to a predetermined behavior and a predetermined sink scan port for always outputting sink data at a predetermined cycle. (A microprocessor; hereinafter referred to as an MPU), and a plurality of light emitting diodes (LEDs) are connected between a predetermined number of row lines (RL1-RL3) and a predetermined number of columns (CL1-CL4). A plurality of light emitting diode arrays (LED1-LED4)-(LED9-LED12) connected in a matrix type, each emitter is connected to a power supply voltage Vcc and each collector is connected to a corresponding row of the light emitting diode array. Each base and the MPU are connected between the respective display data output ports through resistors R1-R3 and driven according to a signal input to the base to supply a power supply voltage Vcc to the row line. 1st, 2nd, 3rd Tran The outputs of the MPU are connected between a plurality of channels (Tr1, Tr2, Tr3) and a predetermined number of sink data output ports of the MPU and the column lines of the LED arrays (LED1-LED4)-(LED9-LED12). And a driver 10 for inputting the sync data output from (O4-O7) to each column line of the light emitting diode arrays LED1-LED4-LED9-LED12.

At this time, the driver 10 in the configuration of FIG. 1 is typically a high darlington array chip.

An anode of each light emitting diode in the light emitting diode arrays LED1-LED4-LED4-LED12 is connected to the row lines RL1-RL3, respectively, and the column lines CL1, CL2 ( CL3) and CL4 are connected to a cathode of each light emitting diode in each of the light emitting diode arrays LED1-LED4-LED9-LED12, and vice versa. The circuit of FIG. 1 is an example of driving twelve light emitting diodes (LEDs), and the port of the MPU should be expanded when the light emitting diodes are extended further.

In the conventional circuit configured as described above, the MPU is assigned to the sink data output ports O4-O7 to display the respective light emitting diodes LED1-LED12 in the light emitting diode arrays LED1-LED4-LED9-LED12. The sync data of "low" is sequentially output in the period of. At this time, the driver 10 amplifies and outputs the outputs of the output ports O4-O7 of the MPU.

That is, the driver 10 amplifies the current of the sync data outputted from the output terminals O4-O7 of the MPU, and applies it to the column lines CL1, CL2, and CL3 of the light emitting diodes LED1-LED22. CL4) is sequentially input to supply sink current to the cathodes of each of the light emitting diodes LED1 to LED2.

At this time, when the MPU outputs "low" sync data to the output terminal O4 to drive the light emitting diode LED1 and outputs "low" display data to the output terminal O1, the light emitting diode LED1. ) Is displayed (on). That is, when the display data of "low" is output from the output terminal O1 of the MPU, the transistor Tr1 is driven "on" so that the first row line RL1 in the light emitting diode array LED1-LED4 has the transistor TR1. Power supply voltage Vcc through the emitter-collector

Therefore, the anode and the cathode of the light emitting diode LED1 are supplied by the power supply voltage Vcc output from the collector of the transistor Tr1 and the sink current of " low " output from the output terminal Q1 of the driver 10. Driven and displayed.

Similarly other light emitting diodes (LED2-LED12) are also displayed under the control of the MPU.

However, the conventional LED driver circuit configured as shown in FIG. 1 has a problem that the MPU cannot be efficiently utilized by allocating an input / output (I / O) port of the MPU to the LED drive. In addition, there has been a problem that a peripheral circuit (transistors Tr1-Tr3) for driving the sink current has to be added, which has increased the number of man-hours.

Accordingly, an object of the present invention is to provide a LED drive method for driving the plurality of LEDs by outputting driving current and sink current using only one latch in a circuit for driving a plurality of LEDs using a microprocessor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of an LED drive according to the present invention, and has a predetermined period with data output ports D0-D3 and sync data output ports D4-D7 for outputting data for displaying an operation state according to a predetermined action. MPU 12 which sequentially outputs the sync data, and outputs a latch signal in the same manner as the sync data output period to a predetermined first terminal, for example, an address latch terminal, and a predetermined number of row lines RL1-RL4. And a light emitting diode array 24 in which a plurality of light emitting diodes LED1-LED16 are connected in a matrix form between the heat lines CL1-CL4 and the display data output ports D0-D3 of the MPU 12. Data input ports DI1-DI8 are connected to the data output ports D4-D7, and output terminals Q1-Q8 are connected to the row lines RL1, RL2, RL3, and RL3 of the LED array 24. (RL4) and column lines (CL1), (CL2), (CL3) and (CL4), respectively, and are connected to the table by the latch signal output of the MPU (12). Data and sink data are latched so that the source current and the row lines RL1, RL2, RL3, RL4 and column lines C1, LC2, LC3 and LCL4 of the light emitting diode array 24 are respectively. The latch circuit 14 outputs the sink current.

At this time, the latch circuit 14 used HCT374 which is a general purpose integrated circuit.

Reference numerals 16-22 are current limiting resistors, which are connected between the data output ports Q1-Q3 of the latch circuit 14 and the row lines RL1 (RL2) (RL3) (CL2) of the LED array. .

FIG. 3 is an operation waveform diagram of FIG. 2, in which the symbols D0-D3 in the drawing denote display data DLED1 (DLED16) output from the MPU 12, and D4-D7 are Δt in a period 4T of the MPU 12. FIG. This is a waveform diagram in which sync data having a period is sequentially output at T main intervals, and ALE is a latch signal of the MPU 12. Q1-Q8 is an output waveform diagram of the latch circuit 14.

An operation example of FIG. 2 will be described in detail with reference to the waveform diagram of FIG.

If the power supply voltage Vcc is supplied to the circuit shown in FIG. 2 now, it resets (initializes) like a normal system which uses an MPU, and outputs an output terminal as shown in FIG. 3 by a program built in the MPU 12. D4, D5, D6, and D7 sequentially output sync data of T periods that become " low " during the? T periods every 4T periods.

At this time, the MPU 12 outputs the latch signal ALE as shown in FIG. 3 every time the " low " sync data is output to the output ports D4-D7 for the? T time. The output period of the latch signal ALE is the same as the output period of the sync data.

Accordingly, the latch circuit 14 is " low " for each? T time from each of the output terminals D4-D7 of the MPU 12, and is " low " sync data T sequentially outputted every 4T periods. By latching and outputting by the latch signal ALE outputted every cycle, the output terminals Q5, Q6, Q7, and Q8 of the latch circuit 14, as shown in FIG. 3, Q5, Q6, Q7, and Q8 during the T period. The sync signal (sink current) of the "low" duration is sequentially output.

That is, the sync data having a period? T is output from the output terminal D4 of the MPU 12 as shown in D4 of FIG. 3, and the address latch terminal ALE is provided at a period of? T in a T period interval as shown in FIG. When a logic "high" signal is output, the latch circuit 14 for inputting the signals receives the "low" sync data input to the input terminal D15 and the "high" address latch signal input to the latch terminal LE. By latching by (ALE), a "low" signal is output to the output terminal Q. At this time, the "low" signal output from the output terminal Q of the latch circuit 14 is maintained until the next address signal ALE is input.

Therefore, as shown in FIG. 3, D4, D5, D6, and D7 from the output terminals D4, D5, D6, and D7 of the MPU 12, sync data is sequentially output every T cycle, and FIG. 3 is an address latch like ALE. When the signal ALE is outputted in the T period, the output terminal Q5, Q6, Q7, and Q8 of the latch circuit 14, which inputs the signal ALE, has a " low " The sync data having the level is converted into the sync data having the level of " low " for the period of T and output.

Therefore, the sync data A, B, C, and D sequentially output from the output terminals Q5, Q6, Q7, and Q8 of the latch circuit 14 are repeated every 4T. When a predetermined behavior signal (for example, a key press signal) is input to the MPU 12 while operating as described above, the MPU 12 outputs data displaying the behavior signal input to the output terminals D0-D4. Output through

For example, if a key signal is input, data for displaying a corresponding key signal input is output. If the light emitting diode displaying the key input is a light emitting diode (LED2) located in the light emitting diode array 24, it is as follows. .

When a key signal corresponding to the light emitting diode LED2 is input, the MPU 12 outputs the display data (D0) to the display data output terminal D0 when the sync data B as shown in FIG. DLED2) is output to logic " 1 " F, and the latch signal ALE is output. At this time, the latch circuit 14 has the same logic as that of the display data DLED2 of the logic " 1 " as shown in FIG. 3, D0, which is output from the output terminals D0 and D6 of the MPU 12, respectively. A row line RL1 of the LED array 24 is latched by the latch data ALE by latching the " low " sync data B by the latch signal ALE. ) And column line CL2 respectively.

Therefore, signals output from the output terminals Q1 and Q6 of the latch circuit 14 are input to the light emitting diode LED2 and the anode and the cathode respectively located in the light emitting diode array 24. That is, the voltage of the "high" level through the resistor 16 is input to the cathode of the light emitting diode LED2, and the sink data of the "low" level such as "B" of FIG. 3 Q6 is input to the cathode.

Accordingly, the light emitting diode LED2 is "on" by the input of the signal as described above to display the key input for T time of the total output period 4T of the sync data.

At this time, in order to maintain the display state of the light emitting diode LED2 for a predetermined time, the logic is output to the output terminal D0 at the time when the sync data B of "low" is output from the output terminal D6 of the MPU 12. The display data DLED2 of 1 " can be continued by writing to the latch circuit 14. FIG.

On the other hand, when the light emitting diodes (LED2) and (LED3) are to be displayed "on", the MPU 12 outputs "low" sync data (B) to the output terminal (D6) for Δt time and outputs after T-Δt time. At the time of outputting the "low" sync data C to the terminal D7, the display data DLED2 of logic "1" is output to the output port D0 for Δt time, and after T-Δt, the logic of "1" is output. This is possible by continuously outputting the display data (DLED3).

As described above, when the MPU 12 writes the display data DLED2 (DLED3) and the sync data B (C) to the switching circuit 14 for Δt time for every T period as shown in FIG. 3, the latch circuit 14 Output terminals Q1 and Q6 and Q7 are respectively delayed by T-Δt for each display data and each sync data of Δt time as shown in FIG.

Therefore, the row line RL1 of the LED array 24 supplies the supply power supply voltage Vcc level while continuously outputting the display data DLED2 (DLED3) of the "high" logic of the output terminal Q1 of the latch circuit 14. The column lines RL2 and RL3 are outputted by displaying the sink current driven by the " low " signals sequentially output from the output terminals Q6 and Q7 of the latch circuit 14 so as to emit light. Do

Accordingly, the MPU 12 may have a margin of T-Δt time immediately after outputting each display data DLED2 and DLED3 for Δt time during the T period, and at this time, the data bus D0- of the MPU 12. D7) can be used for other purposes.

As described above, the present invention outputs the corresponding display data and the sink data from the data bus of the MPU by using a latch circuit in driving a plurality of LEDs, and the corresponding LEDs are displayed by latching the display data. The MPU can be used for other purposes during the time it takes to output the latch signal and output the latch signal, thus making effective use of the MPU.

Claims (1)

In the LED drive method using a microprocessor, it has a predetermined number of data output ports D0-D3 for displaying a state according to a predetermined action, and has a predetermined number of cycles with a predetermined number of sync data output ports D4-D7. The MPU 12 sequentially outputs the sync data and outputs a latch signal to the predetermined first terminal ALE in the same manner as the sync data output period, and a predetermined number of row lines RL1-RL4 and a column line CL1. A plurality of light emitting diodes 24 connected in a matrix form between -CL4) and the display data output ports D0-D3 and the sync data output ports D4-D7 of the MPU 12. The output terminals Q1-Q8 are connected to the data input ports DI1-DI8, and the output terminals Q1-Q8 are connected to the row lines RL1-RL4 and column lines of the light emitting diode array 24 to output the latch signals of the MPU 12. Latching input display data and sync data to Each of the display data output ports of the MPU 12 includes a latch circuit 14 for delaying output of the source and sink currents in the row lines RL1-RL4 and the column lines CL1-CL4 of the array 24. D0-D3) and display data and a latch signal having a? T period respectively output from the first output terminal ALE are outputted in a T period, and the sync data output ports D4-D7 are sync data having a? T period. Is sequentially output at 4T time intervals to supply display data and sync data of the DP-th T periods of the plurality of row lines RL1-RL4 and the plurality of column lines CL1-CL4 of the LED array 24, respectively. LED drive method characterized in that.

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