KR920003346B1 - T.30 protocol command receiving and analysis method - Google Patents

Abstract

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Description

T.30 protocol command reception and analysis method for multi-fax communication

1 is a system diagram applied to the present invention.

2 is a detailed block diagram of the FIU 11 in FIG.

3 is a general HDLC command format diagram.

4 is an interrupt vector table in accordance with the present invention.

5 is a flowchart of an interrupt service routine in accordance with the present invention.

6 is a flow chart of a command analysis routine in accordance with the present invention.

7 is a memory map and data buffer table of each line management table according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception system of a facsimile (hereinafter referred to as a “FAX”), and in particular, to receive a HDLC format command on multiple lines at the same time through a FAX Interface Unit (FIU) capable of processing multiple lines. It's about how you can do it.

As shown in FIG. 1, a system for FAX communication can be seen from patent applications 87-15548 and 89-4110 filed by the same application of the present application, and will be described briefly below.

First, the overall system description will be omitted, and the FIU 11 and FCP 10 will be described. As shown in FIG. 2, the NCU 23 is properly connected to the PABX 103 to provide various devices in the FIU 11. The device that controls the connection.

When a ring comes in from the telephone, a ring detector in the NCU 23 detects the ring and notifies the CPU 14 directly, and the CPU 14 sends a call notification to the MCP 8 that the ring has come, and then the NCU 23 Command to connect the data bus. At this time, when a (Voice) command to receive various types of push button data is received from the MCP (8), the CPU 14 outputs the voice to the user through the CODEC (21) of the corresponding data of the EPROM (18). The user hears the voice and transmits PB data (combination of 0-9, #, *) to DTMF 20 using push button (PB) of telephone. The DTMF 20 converts the analog data into digital, interrupts the INTC 16, writes the PB data to the designated buffer in the RAM 19, and transfers the PB data to the FIFO 17 through the DMAC 15 to transfer the MCP ( To 8). When the voice output and PB data reception is repeated as described above, when all PB data reception is completed, the phone is finally hooked on and a voice output is requested to press the communication button of the FAX 101.

Thereafter, T. 30 protocol communication is performed between the FAX modem and the modem 22 in the FIU 11. At this time, the protocol information is sent and received, such as the type of FAX, line speed, font mode, etc. If this rule is established, the actual FAX image data is transmitted to the FCP 10 using the MODEM 22 and the DMAC 15. Receiving the message information of the MCP (8), the transmission in the unit of block with the PCP (13). When the transmission is over, cut the line. When you want to send the received image data, find a new free line and connect it to the corresponding fax. Then, send the data by the other party's facsimile on a block basis. It is finished. Existing faxes can only communicate in point-to-point format and cannot multiply. In addition, adding various functions to FAX itself is inefficient in terms of price, and therefore, there is a limit in adding a function. In order to overcome such a situation and receive a small and inexpensive FAX service, it is necessary for the FAX user to directly access the MHS (Message Handling System) to receive MHS service.

Accordingly, an object of the present invention is a method of receiving and analyzing T.30 protocol commands for multi-FAX communication in which multiple FAX users can receive MHS service by simultaneously receiving and processing HDLC format commands through a multi-line FIU.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a general HDLC command format diagram, FIG. 4 is an interrupt vector table diagram according to the present invention, FIG. 5 is a flowchart diagram of an interrupt service routine according to the present invention, and FIG. 6 is a flowchart of a command analysis routine according to the present invention. 7 is a memory map and data buffer table diagram of each line management table according to the present invention, (A) is a memory map of the line management table, and (B) is a data buffer table diagram.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 1-7.

First, since the part to be actually described is with respect to FIG. 1, the FIU 11, the configuration of FIG. 2 associated with the present invention will be described. It is composed of necessary DMAC 15, INTC 16, and a plurality of modems 22, and 256K of RAM 19 is used as a memory. Each modem 22 is connected to each channel of the DMAC 15 and the DMAC 15 activates the DMAC 15 when command data is received. The DMAC 15 saves the data in a memory. An interrupt request is made to INTC 16. At this time, the interrupt service routine shown in FIG. 5 is executed by the interrupt generated, and the routine is allocated by processing a corresponding address for each line by a hardware connection. Therefore, when a data reception request is received from each modem 23 to each channel of the DMAC 15, each channel of the DMAC 15 reads one byte of command data from the modem 22 independently of each other, thereby providing RAM (19). Save to the buffer of each line. Each channel of DMAC 15 then requests an interrupt to each channel of INTC 16. At the same time, when an interrupt request comes in, interrupts are processed according to a predetermined order. While the interrupts of the higher rank channels are being processed, the lower rank interrupts are pending, so there is no fear of losing an interrupt. After the execution, the CPU 14 analyzes the received data and performs processing. The following describes the interrupt service routine execution when the interrupt is caused by hardware. That is, COMRECV0, COMRECV1, COMRECV2, COMRECV3,... Assigned to each line in FIG. 5 by the vector table shown in FIG. The routine will run. When the interrupt is generated, INTC 16 carries one of the routines with an interrupt vector address.

The vector table uses an Intel-based assembly language, and sets the vector number 20H corresponding to each channel in the interrupt controller. This is the process of saving the vector address to OXXH.

3 is a format of an HDLC frame recommended in CCITT T.30, and a method of receiving the frame corresponds to the present invention. The preamble 1A of the HDLC frame format refers to about 28H 7EHs that are synchronized to send one command, and non-standard facilitator frame (Non-) in binary coded information. The standard facilities frame (2A) is information that passes only between the same FAX models. The cold subscriber identification frame 3A is its own information, such as a telephone number, and the flag 4A is used for 7EA to sync. Address 5A is set to 0FFH as an address field, and control 6A is 1100 × 000B which can indicate whether it is the first frame or the last frame, and the facsimile control 7A has one Command code indicating what frame a frame is. The facsimile information indicates the degree of speed coding mode image quality, paper width, etc., which is actually communicated information, and the frame checking sequence 8A is 2-byte data for error checking. The facsimile information G1 and G2 Capability 9A are data related only to G1 and G2 and are not serviced here. B asic G3 Capability + Additinal The G3 Capability (10A) is everything you need to send and receive G3.

The interrupt service routine performs the following tasks. As shown in FIG. 7A, the base address of the related table LCTB of the corresponding line is set in the base register BX, where step (1B) corresponds to channel 0 and step (2B) is channel 1 and (3B). Is channel 2, and step 4B corresponds to channel 7, and is line-specific line management tables (LCTBs) shared by the interrupt service routine and the base level routines. After determining the base address, a TCRINT routine is performed in step 5B. The routine receives data such as the preamble 1A and the frame check sequence 8A of FIG. 3 that are actually received without zero delete, and then processes one byte to receive one frame. Perform. When the frame is received, it raises the event to the base level. As shown in FIG. 6 by the interrupt service routine, if an event is received in steps 1E and 2E, in step 3E, after receiving 1 after 5 in the received data, 0 is received. In step 4E, a CRC check is performed. After the CRC check, in step 5E, if a CRC error occurs, the retransmission command is transmitted in step 6E. If there is no error, the command is analyzed in step 7E. 7B shows a command reception buffer for each line.

Before describing the interrupt service routine, the symbols of this routine are described below.

COMRECV0-COMRECVn is the interrupt service routine name, PUSHA is the instruction to save all active registers to the stack, MOV BX, offset LCTB is the instruction to load the address of the line management table into BX, ADD BX, 100H * X is a process of allocating 100H of memory for each line to the line management table to calculate a base address for saving all information about the line. The base address of the line is determined according to the x value.

In addition, TCRINT is the module to be processed when an actual interrupt occurs. MoV DX, [BX + INT_END] notifies the DX of an address to clear the generated interrupt. OUT DX, AL is currently loaded on DX. The interrupt generated by writing the value of AL to the correct address is cleared, the CPU EOI end of interrupt the CPU, POPA restores all registers to the state before the interrupt occurred, and IRET Break out of interrupt handling routine.

AL ← [BX + COMBYT] loads the value of the address pointed to by BX + COMBYT to AL. ROL Al, 1 is the command to left-rotate one bit of the AL register. RCL CL, 1 Is a command to rotate one bit of the CL register, but the carry flag is shifted to bit 0 of the CL register, and [BX + FLAG_CNT] ← saves 1 at the address pointed to by BX + FLAG_CNT. Means.

The BX is a base register, the DX is a data register, the AL is an accumulator low register, and CL is a counter low register.

Next, in the flow of interrupt service routine, in step (1B-4B) in Fig. 5, each of the commands to load the address of the line management table (LCTB) into the BX register is executed, and all the information about the line is saved. Calculate the base address. In step (5B), the interrupt service routine processes when an actual interrupt occurs, and then performs step (6B). In step (6B), an address for clearing the generated interrupt is loaded into the DX register, the generated interrupt is cleared, all the registers are restored to the state before the interrupt occurred while the CPU is end-of-interrupted, and the interrupt processing routine is released. Referring to step (5B), in step (1C), the value of the address indicated by BX + COMBYT is loaded into the AL register, and then step (2C) is performed. In step (2C), it checks whether the AL address is 0FFH and returns if it is 0FFH, and performs step (3C) if it is not 0FFH. In the step (3C), the value of the address indicated by BX + CL_SAVE is loaded into the CL register, the 8 is saved to the AH register, and the step (4C) is performed. In step (4C), it is checked whether the value of BX + SYNC_FLG is 1, and if it is 1, step (5C) is performed. In the step (5C), the instruction to left rotate one bit of the AL register, and the left bit of the CL register to left rotate, but the carry flag is shifted to bit 0 of the CL register, and then performs the step (6C). do. In step (6C), it is checked whether the CL register is 7EH. If it is not 7EH, in step (7C), the value of the CH register is increased by one, and the result is saved in the CH register (8C). In step (8C), it is checked whether the CH register is 8, and if it is not 8, the value of the AH register is decreased by one in step (9C), and then step (6C) is performed again. If the CL register is 7EH in step (6C), check whether the value of the address indicated by BX + LAST_CHK is 0 in step (10C), and if it is 0, save 0 to the CH register in step (11C), and then perform step (12C). Perform.

In step (12C), the value of the AH register is decreased by one, and the result is saved in the AH register. In step (13C), it is checked whether the AH register is zero. If the AH register is not 0, in step 14C, the first bit of the AH register is left rotated and the first bit of the CL register is left rotated, but the carry flag is shifted to bit 0 of the CL register. Increase the value of 1 by storing it in the CH register, and then perform step (12C) again. If the AH register is 0 in step (13C), the CL register value is stored in the address indicated by BX + CLSAVE in step (15C) and returned. If the value of the address indicated by BX + LASTCHK in step (10C) is not 0, the value of CH register is loaded in the DL register in step (16C), 0 is stored in the DH register and CH register, and then step (17C) is performed. do.

In step (17C), the value of the AH register is decreased by one and loaded into the AH register. In step (18C), it is checked whether the value of the AH register is 0. In the step (19C) it is carried out as in step (14C) and then performs step (17C) again. If the value of the AH register is 0, in step 20C, the value of the CX register is loaded at the address indicated by BX + LAST_CHK, and the value of the address indicated by BX + BUF_CNT is loaded at the AL register. In step 21C, if the value of the AL register is less than 5, it is checked to be smaller than step 22C, and if not smaller, step 23C is performed. In step (22C), 0 is stored at the address indicated by BX + LAST_CHK and BX + BUF_OUT and returned.

In step (23C), the AX register is loaded by multiplying the AX register by 8, the AX register is loaded with AX-DX, the AX register is loaded at the address indicated by BX + FRMESIZ, and the BX + FCOMBUF pointed to the AX register. Load into the address, add 32H to the address pointed to by BX + FCOMBUF, load it into the address pointed to by BX + FCOMBUF, load the EVENT Value of E_FRAME to the address pointed to by BX + FAX_EVENT, and then return to step 22C. Perform If the CH register is 8 in step (8C), go to step (1D) of performing a routine for storing data in step (24C) and perform step (1D). In step (1D), load the value of the address pointed to by BX + FCOMBUF into the DI register, load the value of the address pointed to by BX + BUFCNT into the AL register, save 0 to the AH register, and store DI + AX to the DI register. It loads the value of CL register to the address pointed to by DI register, increases the value of the address pointed to by BX + BUF_CNT, loads it to the address pointed to by BX + BUF_CNT, and returns. After performing step (24C), in step (25C), 1 is stored at the address indicated by BX + LAST_CHK, 0 is stored in the CH register, and then step (26C) is performed. In step 26C, the value of the AH register is decreased by 1 and loaded into the AH register to check whether the value of the AH register is 0 in step 27C. If the value of the AH register is 0, in step 28C, the value of the CL register is loaded at the address indicated by BX + CL_SAVE and returned. If the value of the AH register is not 0, step (30C) is performed after step (29C) to step (5C).

In step (30C), check whether the value of the CL register is 7EH, and if it is 7EH, perform step (16C); Perform step 26C) again. If the value of the address indicated by BX + SYNC_FLG in step (4C) is not 1, the same operation as in step (5C) is performed in step (32C). In step 33C, after determining whether the value of the CL register is 7EH, if it is not 7EH, in step 34C, after determining whether the value of the AH register is 0, if it is 0, the step 35C is performed. Perform step 32C). In step 35C, the CL register value is loaded at the address indicated by BX + CL_SAVE and returned. In the case of 7EH in step 33C, step 36C is performed to load the address indicated by BX + Flag_CNT by adding 1 to the address indicated by BX + Flag_CNT and then perform step 37C. In step (37C), if the address value indicated by BX + Flag_CNT is 20H, step (38C) is performed if 20H, and step (39C) if not 20H. In step (38C), 1 is stored at the address indicated by BX + SYNC_FLG, 0 is stored at the address indicated by BX + LAST_CHK, and then step (39C) is performed. In step 39C, the value of the AH register is decreased by one and loaded into the AH register. In step 40C, it is checked whether the value of the AH register is zero.

If the value of the AH register is 0, in step 42C, the value of the CL register is loaded at the address indicated by BX + CL_SAVE and returned. If the value of the AH register is not 0, step (41C) is performed as in step (19C) and step (39C) is performed again.

As described above, T.30 protocol command reception is very slow at 300bps in the multi-line FIU, so it is irrelevant even if the data link layer is processed by software. Therefore, the hardware configuration is simplified, which has the advantage of cost reduction and multi-line processing. By providing the instrument to provide more services to the FAX users, there is an advantage to enable communication using the MHS service.

Claims (2)

In the method of receiving a command in the fax interface unit of facsimile communication, the first process of determining the base address of the management table of the line by the INTC carrying an interrupt vector address when an interrupt occurs, and the value of the AL register is not 0FFH. If the address indicated by BX + SYNC_FLG is not 1, the second step of checking the flag until the address field appears when the CL register is 7EH; and if the value of the address indicated by BX + SYNC_FLG is 1, the CL register is 7EH. If the CH register value is 8 and the CH register value is 8, save the data and check it until the flag is detected. If the CL register value is 7EH, check the flag counter and increase the buffer counter to increase the AL register value. Number of T.30 protocol commands for multi-fax communication, characterized by the fourth process of generating an event Way. In the command analysis method of the fax interface unit of facsimile communication, when an event is received, a reception deciding process for deciding incoming zeros after 1 to 5 in the received data and a retransmission command when a CRC error occurs by performing a CRC check T.30 protocol command analysis method for multiple FAX communication, characterized in that the command analysis process for processing the command if there is no CRC error transmitted.

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