KR920002786B1 - An announcement system with digital signal in electronic switching systems - Google Patents

Abstract

The apparatus includes a central processing and audio storing section (110), a function selecting and controlling section (120), an audio input/output matching section (130), and a testing and warning section (140). The section (110) is connected to both the matching section (130) and the section (120) in such a manner as to control them (120)(130). The (120) is connected to the matching section (130) to control it. The testing and warning section (140) is connected to both the matching section (130) and the feature selecting and controlling section (120) to receive warning signals from the sections.

Description

Digital recording guide device of electronic exchange

1 is a block diagram of the recording guide apparatus of the present invention.

2 is a schematic configuration diagram of a recording guide device of the present invention.

3 is a data buffer direction control circuit diagram.

4 is an input / output signal diagram of a memory control circuit.

5 is an address allocation diagram by a memory control circuit.

6 is an internal configuration diagram of an input / output decoder.

7 is an internal configuration diagram of a repetition time selection circuit.

8 is an internal configuration diagram of a mode selection circuit.

9 is a timing diagram of a continuous operation function.

10 is a timing detail diagram of a start / end operation function.

11 is a timing detail diagram of the instantaneous selection operation function.

12 is a timing diagram and a pupil selection display diagram of a memory division operation function.

13 is an internal configuration diagram of a state output circuit.

14 is a flow chart of the main routine during a schematic functional flow.

15 is a flowchart of an interrupt routine during a schematic functional flow.

16 is a detailed diagram of a channel assignment circuit.

17 is an input / output signal timing diagram of a channel assignment circuit.

18 is an internal configuration diagram of a handset and a tape recorder matching circuit and an A / D D / A conversion circuit.

19 is an internal configuration diagram of a series / parallel parallel / serial conversion circuit.

* Explanation of symbols for main parts of the drawings

110: central control and voice storage unit 120: function selection and control unit

130: voice input and output matching unit 140: test and alarm circuit unit

211: central processing unit 212: data buffer

213: address buffer 214: control buffer

215: memory control circuit 216: ROM

217: RAM 218: clock generation circuit for the central processing unit

221: input / output decoder 222: repetition time selection circuit

223: mode selection circuit 224: status output circuit

225: interrupt generation circuit 231: serial / parallel parallel / serial conversion circuit

232: A / D D / A Conversion Circuit

233: Handset and Tape Recorder Matching Circuit

234: channel assignment circuit 241: test clock generation circuit

242: alarm circuit 520: bank memory

700, 800: Input buffer 720: Rotary switch

1300: output latch circuit 1310: light emitting diode part

1610, 1611: synchronous binary counter 1620: line decoder

1810: transmit and receive filter

1820: Encoder / Decoder of Pulse Coded Modulation

1910: serial / parallel conversion circuit 1911: parallel / serial conversion circuit

1920: data selection circuit 1930: input buffer

1940: Output buffer S0 to S7: switch

The present invention relates to a recording guide device for recording and reproducing a voice announcement for guiding a situation such as a missing or residing state and a failure state occurring during call processing in all electronic exchanges. The present invention relates to a digital recording guide device of an electronic exchange device in which all types of control functions are configured in an electronic form of a digital type to improve sound quality and durability, and to select various functions by an external control device.

The recording guide device uses a large number of analog or digital methods for recording and transmitting audio. Generally, first, analog recording, analog playback, and second, digital recording, analog, playback, and third, digital recording, digital, playback. It consists of three types of methods.

The first and second analog reproduction transmission methods require a matching device for converting an analog audio output into a digital signal to be used in a digital type electronic exchange. In particular, the first method uses a magnetic disk or a magnetic tape to perform the storage and reproducing method of voice in an analog form, resulting in deterioration of sound quality and short life due to mechanical wear of the storage medium.

In the second method, the analog voice is received through a microphone or a cassette recorder, converted into a digital voice, and stored in a storage medium, so that wear and sound quality deterioration can be avoided, but the voice is output in analog form for use in a digital electronic exchanger. In order to achieve this, an analog-to-digital converter is required, which results in deterioration of sound quality.

In the third method, the storage, playback, and transmission methods are digital, so that the disadvantages of wear and tear of the storage media of the first and second methods, additional elements of the analog-digital converter, and subsequent deterioration of sound quality can be avoided. Digital time-division electronic exchange that uses Pulse Code Modulation (PCM) method such as Delta Modulation (DM) or Differential Pulse Code Modulation (DPCM) to reduce the capacity of storage media. In order to be applied to the audio encoding method, the data encoded in another method must be converted into an analog voice, and then converted into a pulse encoding modulation method. Otherwise, a encoding conversion device for converting a different encoding method into a pulse encoding method is required. A circuit is needed and the deterioration of sound quality Is generated is generated a problem such as a structural change in accordance with the economical efficiency decreases and the matching unit Add.

The present invention solves the above problems and converts the voice signal from the microphone or cassette recorder into a digital voice signal by means of a Pulse Coded Modulation (PCM) to match the encoding method of the digital electronic exchanger and stores it in a storage medium. The present invention has been made to improve the sound quality and improve the disadvantages of the conventional apparatus by reproducing and transmitting the digital voice to the time division multiplex channel by the pulse coding modulation method required by the following. same.

The apparatus of the present invention is designed to perform the operation of the recording guide device by the continuous operation, the start / end operation, the instantaneous selection operation, the memory division operation, etc. by a switch inside the device or an external control device.

1 is a block diagram of the recording guide apparatus of the present invention, the central control and voice storage unit 110, the functional selection and control unit 120, the voice input and output matching unit 130, the test and alarm circuit unit 140, etc. The central control and voice storage unit 110 controls the function selection and control unit 120 and the voice input / output matching unit 130. The function selection and control unit 120 controls the voice input and output. The matching unit 130 is controlled, and the test and alarm circuit unit 140 receives an alarm signal from the function selection and control unit 120 and the voice input / output matching unit 130 without the central control.

2 shows the recording guide device of the present invention in more detail. The central control unit and the voice storage unit 110 include the central processing unit 211, the data signal buffer 212, the address signal buffer 213, and the control signal buffer. 214, a memory controller 215, a ROM 216 and a RAM 217, a clock generator 218 for a central processing unit, and the like, and the function selection and control unit 120 repeats the input / output decoder 221 and the repetition time. And a selection circuit 222, a mode selection circuit 223, a status output circuit 224, and an interrupt generation circuit 225. The voice input / output matching unit 130 includes a series / parallel and a parallel / serial conversion circuit 231. And analog / digital and digital / analog conversion circuits 232, handset and tape recorder matching circuits 233, and channel assignment circuits 234, and the test and alarm circuit unit 140 includes a test clock generation circuit 241 and It consists of an alarm circuit 242.

(Machine Cycle One),

(Memory Reguest),

(Input/Output Reguest),

(Memory Read),

(Memory Write),

(Refresh)]가 제어버퍼(214)에 연결되어 동작된다.The central processing unit 211 of the central control and voice storage unit 110 is an 8-bit general purpose central processing unit. The 8-bit bidirectional data signals D0 to D7 are connected to the data buffer 212 and the 16-bit address. Signals A0 to A15 are connected to the address buffer 213 and a 6-bit control signal [

(Machine Cycle One),

(Memory Reguest),

(Input / Output Reguest),

(Memory Read),

(Memory Write),

(Refresh)] is connected to the control buffer 214 is operated.

,

신호의 3신호가 상기 데이터버퍼(212)의 방향을 결정한다.The purpose of using the data buffer 212, the address buffer 213, and the control buffer 214 is to supply sufficient current to the signals so as to drive elements connected to each of the signals. An interrupt signal is supplied to the CPU 211 from the function generator and the interrupt generator 225 of the control unit 120, and a clock signal having a frequency of 2.44 MHz is supplied from the clock generator circuit 218 for the CPU. Of control signals

,

Three signals of the signal determine the direction of the data buffer 212.

)는 송수신 제어신호 입력단자이다.3 shows the direction control circuit of the data buffer 212. When the data is read from the external circuit 301 of the CPU 211 to the CPU, the output of the AND gate 312 is low. When the data buffer 212 is in the forward direction and the output of the AND gate 312 is high, the data buffer 212 is transmitted from the CPU 211 to the external circuit 301. Here, the terminal S / of the data buffer 212

) Is a transmission / reception control signal input terminal.

,

,

)(402) 및 메모리 뱅크 선택방법으로 64Kbyte 용량의 메모리 뱅크를 4개까지, 즉 256Kbyte까지 선택할 수 있도록 제어하는 확장 어드레스신호(P1,P2)(403)로 구성되며 상기 제어신호중 리프레시(

)신호는 다이나믹 메모리를 사용함에 따라 리프레시 동작을 행해야 하므로 256Kbyte 용량의 메모리를 리프레시할 수 있도록 새로운 리프레시 신호를 발생시킨다.4 shows an input / output signal of the memory controller 215. The input signal is a 4-bit high-order address signal (A12 to A15) 401 and a 3-bit control signal for distinguishing the address addresses of the ROM and the RAM.

,

,

402 and expansion address signals (P1, P2) 403 for controlling up to four 64 Kbyte memory banks, that is, up to 256 Kbytes, by the memory bank selection method.

Since the refresh operation must be performed according to the dynamic memory, a new refresh signal is generated to refresh the 256-Kbyte memory.

(404)와 RAM의 어드레스 다중화를 위한 어드레스 선택신호

및 다이나믹 메모리의 횡축 어드레스 선택신호(

; Column Address Strobe), 종축 어드레스 선택신호(

: Row Address Strobe), 데이터 버스의 방향선택신호(

: Data Bus Direction), 새로운 확장어드레스신호(P1', P2'), 새로운 리프레시 신호(

)의 8비트 RAM 제어신호(405)로 구성된다.The output signal of the memory control circuit 215 is a 1-bit ROM selection signal.

404 and address selection signal for address multiplexing of RAM

And the horizontal axis address selection signal of the dynamic memory (

; Column Address Strobe), Vertical Axis Address Select Signal (

: Row address strobe), direction selection signal of data bus (

: Data Bus Direction), new extended address signals (P1 ', P2'), new refresh signals (

8-bit RAM control signal 405.

When the circuit configuration for multiplexing the address is a dynamic RAM (DRAM), the address is divided so that the entire address signal is divided into a horizontal axis address and a vertical axis address. The circuit for selecting a data direction is a data signal line of a central processing unit. Since these two-way transmission and reception functions, the direction of the data input and output signal of the RAM circuit is controlled to match this.

는 ROM에 연결되고 상기 어드레스 선택신호

와 횡축/종축 어드레스 선택신호

, 데이터버스 방향 선택신호(

), 새로운 확장 어드레스신호(P1', P2') 및 새로운 리프레시 신호(

)는 RAM 회로에 연결된다.The ROM selection signal

Is connected to the ROM and the address selection signal

And horizontal / sub axis address selection signal

, Data bus direction selection signal (

), New extended address signals P1 'and P2', and new refresh signals (

) Is connected to the RAM circuit.

)가 이용된다.In the ROM circuit, a general 32Kbyte erasable programmable read only memory (EPROM) is used, and as the address signal, a signal of lower 12 bits (A0 to A11) is used, and 8 bits of data (D0 to 1) which are the data signals. D7) and ROM select signal (

) Is used.

5 is a diagram illustrating a memory address allocation state by the memory controller 215. The address allocation is performed by using an 8Kbyte area 510, which is a use area of a central processing unit, and four memory banks of 64Kbyte capacity, which is a voice data storage area. The configured guide message storage area 520 is used so that only 56Kbytes are used instead of 8Kbytes for each bank.

At this time, the bank is selected by the extended address signals P1 and P2.

Specifically, the ROM area 511 in which the control program of the CPU is stored and the stack and data storage area 512 used during the operation of the CPU are 0000H (regardless of the bank selection signal). H is 4 Kbytes up to 1FFFH at the hexadecimal address, and the stack and data storage area 512 uses 4 Kbytes from 1000H to 1FFFH.

Therefore, the remaining 56Kbytes except 8Kbytes of 64Kbyte memory capacity per bank can be used, and a total of 224Kbyte recording guide messages can be stored by four banks 521 to 524. At this time, if P1 = 0 and P2 = 0 of the extended address signals P1 and P2, bank 1 521 is P1 = 1 and P2 = 0, bank 2 522 is P1 = 0 and P2 = 1 bank. If three 523 are P1 = 1 and P2 = 1, then bank 4 524 is selected, respectively.

,

.

,

)를 조합하여 입출력회로들을 구분 선택하여 주고 상기 반복시간 선택회로(222)는 안내메시지를 녹음 및 재생해주는 시간을 지정해주는 입력회로이며 상기 모드선택회로(223)는 연속동작과 시작/끝동작, 순간선택동작 및 메모리 분할동작을 선택해주는 입력회로이고 상기 상태 출력회로(224)는 저장된 안내메시지의 손상여부 표시와 반복시간의 시작점 지시, 녹음가능상태 표시, 메시지출력상태 표시, 녹음/재생의 표시 및 선택, 확장어드레스(P1,P2)를 결정해주는 출력회로며 상기 인터럽트 발생회로(225)는 8KHz마다 인터럽트를 발생시켜 중앙처리장치에 전달해주는 기능을 수행한다.The function selection and control unit 120 of FIG. 2 includes an input / output decoder 221 repetition time selection circuit 222, a mode selection circuit 233, a state output circuit 224, an interrupt generation circuit 225, and the like. The input / output decoder 221 includes the lower address signals A0 to A3 and the control signal of the central processing unit.

,

.

,

And select the input and output circuits by combining the input and output circuits. The repetition time selection circuit 222 is an input circuit for designating a time for recording and playing back a guide message. The mode selection circuit 223 is a continuous operation and a start / end operation, It is an input circuit for selecting the instant selection operation and the memory division operation. The state output circuit 224 indicates whether the stored guidance message is damaged or not, and indicates the starting point of the repetition time, the recordable status display, the message output status display, and the recording / playback display. And an output circuit for determining selection and expansion addresses P1 and P2. The interrupt generating circuit 225 generates an interrupt every 8 KHz and transmits the interrupt to the central processing unit.

,

,

,

)를 이용하여 입출력 디코더 자체의 기능을 제어한다.6 illustrates the input / output decoder 221 in detail. The repetition time selection circuit 222 and the mode selection circuit 223 using the address signals A0 to A2 and the oA gates 601 to 605 of the central processing unit. And five input / output circuits such as a status output circuit 224, a parallel / serial conversion circuit, and a series / parallel change film 231, and the address signal A3 and the control signal (

,

,

,

) To control the function of the I / O decoder itself.

)에 의하여 제어되고 상기 오아게이트(603)(605)는 제어신호(WR)에 의하여 각각 제어된다.At this time, the output of the oar gate 601 of the output signals of the oragate (601 ~ 605), the repetition time selection circuit 222, the output of the oragate 602 is the mode selection circuit 223, the oragate 603 Outputs of the state output circuit 224 and the output of the oragate (604) 605 controls the series / parallel and parallel / serial conversion circuit 231, respectively, the oragate (601) (602) (604) ) Is the control signal (

Are controlled by the control signal WR, respectively.

FIG. 7 is an internal circuit diagram of the repetition time selection circuit 222 and includes an input buffer 700, a resistor 710, and a rotary selection switch 720.

Here, the recording / playback repetition time selection is selected in 8 steps at 3.5 second intervals from 3.5 seconds to a maximum of 28 seconds, and the recording / playback repetition time as the rotary switch 720 is selected from the contact point S0 to the contact point S7. This is selected from 3.5 to 28 seconds.

In this case, the resistor unit 710 connected between the signal line from the switch contact S0 to the contact S7 and the power supply (+ V) has a high state when the input buffer 700 is not connected to the contact point. It consists of pull-up resistors for stable detection.

In addition, a repetition time selection circuit selection control signal for controlling the input buffer 700 is received from the input / output decoder 221 and connects 8-bit data D0 to D7 to the data buffer 212.

FIG. 8 is an internal configuration diagram of the mode selection circuit 223, which is composed of an input buffer 800, a switch unit 810, and a resistor unit 820. The input buffer 800 is selected by an input / output decoder 221. When selected by receiving the circuit selection signal, the operation function is determined by reading the input buffer value determined by the switch unit 810.

The switch S0 of the switch unit 810 selects the continuous operation and the start / end operation functions, the switch S1 selects the instantaneous selection operation function, and the switches S2 to S5 select the memory division operation function. do.

In addition, the switch S6 is a switch to start recording, and when connected and disconnected, reads the voice data from the voice input / output matching unit at 8KHz sample period and performs the recording function in the selected mode for a predetermined repetition time.

According to the operation of the switch unit 810, the input buffer 800 connects 8-bit data D0 to D7 to the data buffer 212.

FIG. 9 is a timing detail of the continuous operation function of FIG. 8, while the recording guide device continuously selects the signal 9a of the repetition time selection circuit 222 while the switch SO of FIG. The announcement message 9b is replayed and sent out at a time specified by.

FIG. 10 is a detailed timing diagram of the start / end operation of FIG. 8, and when the start / end operation is desired, the switch S0 of FIG. 8 is connected to ground, and the recording guide message (b) starts transmitting. If the switch S0 is disconnected from the ground, the playout operation is interrupted and the function is performed.

FIG. 11 is a detailed timing diagram of the instantaneous selection operation of FIG. 8, and the time determined by the output signal a of the repetitive time selection circuit 222 is immediately disconnected after the switch S1 of FIG. 8 is connected to ground. Only once during the announcement message (b).

12 is a timing diagram (A) and an operation selection table (B) of the memory division operation function of FIG. 8, wherein switch S2 of FIG. 8 selects memory bank 1 for storing the guide message of FIG. S3 selects bank 2, switch S4 selects bank 3, and switch S5 selects bank 4, respectively.

The apparatus of the present invention uses a 64 kbps (Kilo bit Per Sec) pulse encoding modulation method having an 8 KHz sample period of speech. Thus, a guide message of 7 seconds is stored for each bank.

Therefore, in the case of the memory partitioning method, as shown in FIG. 12, at least 7 seconds of announcement messages can be stored and played back in four different types, and one kind of messages of up to 28 seconds can be stored and played back. You can store and play back messages efficiently and flexibly.

FIG. 13 is a diagram illustrating an internal configuration of the state output circuit 224. The resistance unit includes a repetition time start signal 1301, a recordable state display 1302, a guide message damage display 1303, and a message output state display 1304. Through 1320, the light emitting diode unit 1310 is turned on or off to inform the operator.

The indication message damage indication 1303 can be known by acquiring a checksum of data stored in a memory during recording operation and then finding a checksum again when playing the same, and in this case, a message damage indication signal. Is generated and sent to the alarm circuit 242 to light up the light emitting diode for indicating whether the light emitting diode unit 1310 is damaged.

Meanwhile, the recording / playback display signal 1305 is connected to the parallel / serial conversion circuit 231 of the voice input / output matching unit 130 by detecting the recording start signal of the mode selection signal of FIG. The extended address signals P1 and P2 are connected to the RAM circuit 217 and used as the memory bank selection signal as shown in FIG.

The interrupt generation circuit 225 uses a general counter / timer circuit to match the digital encoding of the audio signal to the voice input / output matching unit 130 or the voice input / output matching unit 130 in accordance with a pulse encoding modulation scheme having an 8 KHz sample period. An interrupt signal generation circuit for designating a period of inputting and outputting a digital voice sample of the central processing unit 211 to 8 kHz so as to synchronize.

FIG. 14 and FIG. 15 are schematic functional flow charts of the present invention to jump from the main routine to the interrupt routine in accordance with the 8KHz interrupt signal to perform voice input operation (recording) and voice output operation (reproduction).

As shown in FIG. 14, the main routine of the apparatus is as follows.

When the recording guide device is powered on or reset in step (1), device initialization (step 2) is performed. In this step, mode selection, repetition time selection, melting state flag reset, repetition time initialization flag resetting, Repeat time counter setting, etc. In step (3), the mode selection and repetition time selection function are for inputting the changed mode and repetition time. In step (4), the recording state flag is set in step (5) if the recording is started by detecting whether or not recording is started. And repeating the time-initializing flag setting and circulating to the (3) step, and if the recording is not started, that is, during playback or recording in the (5) step, it is circulated to the (3) step.

In this way, the interrupt routine is executed every 125 microseconds after the main routine is executed.

15 is a flowchart of an interrupt routine. If an interrupt occurs in step (1), the recording status flag is checked in step (2). If the repeat time initialization flag is checked in step 3) and set (＂1＂), set the repeat time counter to the repeat time in step (4), and then repeat step (5) after the reset initialization flag is reset (＂0＂). Perform.

If the repetition time initialization flag is reset in step (3), go to step (5), input the message in the serial / parallel conversion circuit 231, and then enter the input message in step (6). Remember in memory

Then, in step (7), decrease the repetition time counter value by 1 and check in step (8) the repetition time counter value. If the value is 0, reset the recording status flag in step (9), and then (14). Terminate the interrupt in step).

If the repetition time counter value is not 0, the interruption is terminated at step (14) and the process returns to the main routine.

On the other hand, if the recording state flag in step (2) is 0, it indicates that the playback operation is being played back. In step (10), the counter value is repeated in step (1) if the counter value is 0 and the counter value is 0. Set the selected repetition time in the main routine and proceed to step (12). If the repetition time counter value is not 0 in step (10), go directly to step (12) and read the stored message from the memory in step (13). A message is output to the parallel / serial conversion circuit 231 and the step (7) is performed.

As shown in FIG. 2, the voice input / output matching unit 130 includes a serial / parallel parallel / serial conversion circuit 231, a channel assignment circuit 234, a handset and a tape recorder matching circuit 233, and A / DD / A. The serial / parallel parallel / serial conversion circuit 231 matches the digital voice signal to match the signal pattern of the digital electronic exchange using a pulse encoding modulation method of 64 Kbps. The channel assignment circuit 234 generates a frame synchronization signal to carry a digital voice signal on a designated channel of a time division multiplexed voice signal line in 32 time slots (times or channels).

The handset and the tape recorder matching circuit 233 function to match the input and output of analog voice signals through the handset and the tape recorder, and the A / DD / A conversion circuit 232 converts the analog signal into a digital signal or digitally. It converts a signal into an analog signal.

In addition, the channel assignment circuit 234 receives the system clock and frame synchronization signals from the exchange system and generates 16 channel allocation frame synchronization signals. The channel assignment circuit 234 uses 32 frames on the PCM subhighway by the frame synchronization signal delay method. The lower 16 channels (channels 0 through 15) can be selected.

FIG. 16 is an internal configuration diagram of the channel assignment circuit 234. A synchronous 4-bit binary counter 1610, 1611, a line decoder 1620, and a switch receiving a system synchronization signal 1601 and a frame synchronization signal 1602 are shown in FIG. When the switch S1 is connected with the switch S2 disconnected by configuring the S1 and the S2, the output channel is selected through the decoder 1620 and the channel 0 to the channel 7 are selected, and the switch S1 is If the switch (S2) is connected while disconnected, the channel 8 to channel 15 are output as the output channel.

At this time, the condenser 1605 removes the noise component of the high frequency pulse generated by the decoder 1620.

17 is an input / output signal timing diagram of the channel assignment circuit 234. The system clock a uses a frequency signal of 2.048 MHz (transmission rate 2.048 Mbps) and the frame synchronization signal b is 8 KHz (transmission rate 8 Kbps). Time-division multiplexing of 32 channels using a frequency signal, and in case of an audio signal of 64Kbps (sample frequency is 8KHz, 8 bits per sample) pulse-coded modulation method, each sample is 8 bits, which is one sample for each channel in one frame. Assigned.

Therefore, the frame synchronization signals C 'to C for each channel are delayed by eight system clock cycles.

FIG. 18 is a block diagram of the handset and the tape recorder matching circuit 233 and the A / DD / A conversion circuit 232. The encoder / decoder 1820 of the 64 Kbps pulse encoding modulation method and the filter having a bandwidth of 300 to 3400 Hz are shown in FIG. 1810, tape recorder tweets 1801, and handset tweets 1802 and 1803. FIG.

The tweet 1801 is used for a tape recorder, and when a single-head plug for a cassette tape recorder is inserted to record a guide message from a cassette tape recorder, the contacts 2 and 3 of the tweet 1801 are connected to the plug and simultaneously The contact 1 and the contact 2 are disconnected.

In the state where the plug of the tape recorder is removed from the tweet 1801, the contact 1 and the contact 2 are connected so that the contact 1 of the tweet 1803 is connected to the contact 1 and the contact 1 of the tweet 1801. It is connected to analog ground through 2).

The capacitor C1 connected to the contact 3 of the jack 1801 is a capacitor for blocking a DC current from a DC power source.

The tweets 1802 and 1803 are for handset tweeters, one of the handset twin head plugs is connected to the contact 1 of the tweet 1802 and the contact 1 of the tweet 1803, and the other plug is the tweet 1802. It is operated by being connected to the contact (2) of the contact and the contact (2) of the jack 1803.

A power supply (-V) connected to the jack 1802 supplies a DC current to the carbon microphone type transmitter through a resistor R1, and the analog voice signal inputted through the transmitter or the tape recorder is input to the variable resistor VR. The size is adjusted and input to the transmission terminal of the transmission and reception filter 1810.

The capacitor C2 connected to the input side of the transmission filter 1810 is a DC current blocking capacitor.

The filter 1810 is classified into a transmitting filter and a receiving filter, wherein the transmitting filter is a bandpass filter having a 300 to 3400 Hz bandwidth, and the receiving filter is a lowpass filter having a 3400 Hz blocking characteristic.

The output signal of the receiving filter can be driven by directly attaching a 600-tone receiver. The reason that the input terminal of the transmitting filter is terminated with the analog ground by the resistor R2 is because the classification path made at the input terminal of the filter operational amplifier is This is because it improves the operating conditions and reduces the amount of current flowing into or out of the input terminal so that the filter is not easily aged.

The capacitor C3 and the resistor R3 between the output of the transmission filter 1810 and the input of the encoder 1820 are for matching.

The digital audio data output signal 1805 of the encoder / decoder 1820 is a digital audio signal of 65 Kbps pulse coded modulation method, which is a channel frame synchronization signal supplied from the system clock 1807 and the channel assignment circuit 234. The output data strobe signal 1804 is normally kept in a high state, and is kept low for the time that the digital voice data 1805 is outputted, and the digital voice is assigned to the designated channel. This function informs the outside that data is being output.

The digital voice data input signal 1806 receives a serial digital voice signal from the parallel / serial conversion circuit 231 when the device of the present invention performs a reproducing operation so that the operator can listen to the guide voice message reproduced through the handset tweeter. It is the operator monitoring signal that can monitor the voice signal recorded by the operator through the feedback loop when recording the guidance message through the tape recorder or the handset.

19 is an internal configuration diagram of the serial / parallel parallel / serial conversion circuit 231, which is a serial / parallel conversion circuit 1910 which is a voice data input circuit used in a recording operation, and a parallel that is a voice data output circuit used in a reproducing operation. And a serial conversion circuit 1911, data selection circuit 1920, and input / output buffers 1930 and 1940.

The conversion circuits 1910 and 1911 receive the system clock 1903 and the channel frame synchronization signal 1904 from the channel assignment circuit 234 and input / output of FIG. 6 to select the conversion circuits 1910 and 1911. The output signal from the decoder 221 and the recording / playback display signal from the state output circuit of FIG. 13 are used.

The serial / parallel conversion circuit 1910 receives a pulse-coded modulated digital voice signal 1902 in series from the A / DD / A conversion circuit 232 and receives an output data strobe 1910, a system clock 1903, and a channel frame. The synchronization signal 1904 is received to convert serial digital data into parallel data so that the central processing unit 211 can read it.

The parallel / serial conversion circuit 1911 receives the parallel audio data input from the CPU 211 or the serial / parallel conversion circuit 1910 to the system clock 1903 and the channel frame synchronization signal 1904. Outputs a serial pulse-coded modulated digital audio signal (1905) 1906 to an audio signal line of an A / DD / A conversion circuit 232 or an exchange system on a time-division multiplexed channel.

The data selection circuit 1920 outputs 8 bits outputted from the serial / parallel conversion circuit 1910 so as to form a feedback loop for monitoring the contents recorded by the operator when the recording is performed according to the recording / playback display signal 1907. In the case of the reproducing operation, 8 bits of parallel data inputted through the output buffer 1940 from the central processing unit 211 are selected and converted into serial digital data.

The test and alarm circuit unit 130 is composed of a test clock generation circuit 241 and an alarm circuit 242, the test clock generation circuit 241 is to test the function of the recording guide device of the present invention before being connected to the exchange system. For this purpose, the system clock and channel frame sync signal are made 2.048MHz and 8KHz inside the device.

The alarm circuit 242 receives the stored message damage display signal from the state output circuit 224 and the analog voice signal from the A / DD / A conversion circuit 232, and reproduces the analog voice that is reproduced when there is a message corruption. When the signal is below the specified level (including no signal), the alarm collecting device of the exchange system sends an alarm signal regarding the abnormality of the recording guide device and operates the light emitting diode to inform the operator.

The level value specified here indicates that the size of the audio signal is small enough to be hard to be heard by the ear. The value is -30dBm to -40dBm and the value used in this device is -30dBm.

As described above, by reproducing and transmitting digital voice to the time division multiplexing channel based on the pulse encoding modulation method required by the exchange, the disadvantages of the conventional device are improved and the sound quality is improved. The elimination of the matching circuit for the electronic exchange reduced the cost of ancillary equipment.

In addition, it is designed to perform the operation of the recording guide device as a continuous operation, a start / end operation, a moment selection operation, a memory division operation by a switch inside the device or an external control device, so that it can be flexibly operated according to a user's request. There is an advantage.

Claims (15)

In the recording eyepiece device of the electronic switch, the central control and voice storage unit 110, the function selection and control unit 120, the voice input and output matching unit 130, the test and alarm circuit unit 140, and the central control and The voice storage unit 110 is connected to the function selection and control unit 120 and the voice input and output matching unit 130 to control the function selection and control unit and the voice input and output matching unit, and the function selection and control unit 120 matches the voice input and output matching. It is connected to the voice input and output matching unit 130 to control the unit, the test and alarm circuit unit 140 is the function selection and control unit 120 to receive the alarm signal from the function selection and control unit and the voice input and output matching unit without the central control. And a voice input / output matching unit (130) to receive an analog voice signal and output a processed digital voice signal. According to claim 1, wherein the central control and voice storage unit 110 inputs the data buffer 212 and the 16-bit address signal receiving the 8-bit bidirectional data signal to the 8-bit general purpose central processing unit 211 A memory control circuit 215 which connects a receiving address buffer 213 and a 6-bit control signal and a receiving control buffer 214 and a central processing unit clock generation circuit 218 to control ROM and RAM, respectively. The digital recording guide device of the electronic exchange, characterized in that the memory device is connected to the ROM (216) and RAM (217) to be operated by a bidirectional data signal, an address signal and a control signal. The input / output decoder 221 according to claim 1 or 2, wherein the function selection and control unit 120 selects input / output circuits by combining lower address signals and control signals of the central processing unit 211, and a guide message. Repeated time selection circuit 222 for designating the time for recording and playback, mode selection circuit 223 for selecting continuous operation, start / end operation, instant selection operation, and memory division operation, and whether the stored guidance message is damaged or not. Status output circuit 224 which determines the start point indication of the display and repeat start points, the recordable status display, the message output status display, the display and selection of recording / playback, and the expansion address (P1) (P2), and interrupts every 8 KHz. Digital recording guide device of the electronic exchange, characterized in that consisting of the interrupt generation circuit 225 to generate and deliver to the central processing unit (211). The voice input / output matching unit 130 and the serial / parallel parallel / serial conversion circuit 231 for matching digital voice signals to match a signal pattern of a digital electronic exchange using a pulse code and a modulation method. And an A / DD / A conversion circuit 232 for converting analog and digital signals according to input and output, and a handset and tape recorder matching circuit for matching input and output of analog audio signals through a handset and a tape recorder ( 233) and a channel assignment circuit (234) for generating a frame synchronization signal to carry a digital voice signal on a specified channel of a time division multiplexed voice signal line in 32 channels. The test and alarm circuit unit 140 and the test clock generation circuit 241 for generating a system clock and channel frame synchronizing signal inside the device to test the function of the recording guide device before being connected to the switching system. When the storage message corruption indication signal from the status output circuit 224 and the analog audio signal from the A / DD / A conversion circuit 232 are received and there is a message corruption and the analog audio signal to be reproduced is below a prescribed level. And an alarm circuit (242) for transmitting an alarm signal relating to an abnormality of a recording guide device to an alarm collecting device of an exchange system and operating a light emitting diode to inform an operator. 3. The data buffer 212 according to claim 2, wherein the data buffer 212 is connected to the AND gate 312 and the oragate 311 control signal (

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And the data buffer 212 is configured to be in a reception state or a transmission state according to the output of the AND gate 312. 3. The memory control circuit 215 of claim 2, wherein the memory control circuit 215 is a four-bit upper address signal and a control signal.

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And extended address signals P1 and P2 to distinguish between the address addresses of the ROM 216 and the RAM 217, select a memory bank, and generate a new refresh signal capable of refreshing the dynamic memory. Digital recording guide device of the electronic exchange. The input / output decoder 221 of claim 3 is configured to include an address signal and a control signal.

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Select the repetition time selection circuit 222 according to the output of the oragate 601 to 605, or the mode selection circuit 223, the status output circuit 224, the series / parallel parallel / serial conversion circuit 231 Digital recording guide device of the electronic exchange, characterized in that configured to select each. 4. The repetition time selection circuit 222 is composed of an input buffer 700 and a rotary switch unit 720, and the recording / playback repetition time is at least 3.5 seconds depending on the connection of the switch contacts S0 to S7. Digital recording guide device of the electronic exchange, characterized in that the selection is made in 3.5 second intervals up to 28 seconds. 4. The mode selection circuit 223 is composed of the input buffer 800 and the switch unit 810, and is determined by the switches S0 to S6 when the mode selection circuit is selected by the input / output decoder 221. A digital recording guide device of an electronic exchange, characterized in that for reading an input buffer value and performing an operation function accordingly. 4. The status output circuit 224 is composed of an output latch buffer 1300 and a light emitting diode unit 1310. The repetition time start signal, a recordable state display, a guide message damage display, a message output state display, and the like. Digital recording guide device of the electronic switch, characterized in that to inform the operator to turn on / off the light emitting diode unit (1310). 5. The channel assignment circuit 234 is comprised of a synchronous binary counter 1610, 1611, a line decoder 1620, switches S1, S2, and a system clock and frame synchronization signal from an exchange system. Digital recording of the electronic switch, characterized in that 16 channel assignments are made to make a frame synchronization signal, and 16 subchannels among 32 channels on the pulse code and modulation subhighway can be selected by the frame synchronization signal delay method. Guide device. The handset and the tape recorder matching circuit 233 and the A / DD / A converter circuit 232 are connected to the filter 1810 and the encoder / decoder 1820 to connect the handset and the tape recorder to the playback operation. The operator can listen to the guidance voice message which is reproduced through the handset jack when the serial digital voice signal from the parallel / serial conversion circuit is used.When the operator records the guidance message through the tape recorder or handset, Digital recording guide device of the electronic exchange, characterized in that for monitoring the state of the audio signal recorded through the feedback loop. 5. The serial / parallel parallel / serial conversion circuit 231 is a serial / parallel conversion circuit 1910 which is a voice data input circuit used in a recording operation, and a parallel / parallel / output circuit which is used in a reproducing operation. And a serial conversion circuit (1911), a data selection circuit (1920), an input / output buffer (1930), (1940). 15. The parallel data output from the serial / parallel conversion circuit (1910) according to claim 14, characterized in that the data selection circuit (1920) is configured to configure a feedback loop for the operator to monitor the recording when the recording is performed according to the recording / playback display signal. And selecting the parallel data inputted through the output buffer (1940) from the central processing unit and converting the serial digital data in the case of the reproducing operation.

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