KR920001490Y1 - 자석이 내장된 넥타이 - Google Patents

자석이 내장된 넥타이 Download PDF

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Publication number
KR920001490Y1
KR920001490Y1 KR2019900001233U KR900001233U KR920001490Y1 KR 920001490 Y1 KR920001490 Y1 KR 920001490Y1 KR 2019900001233 U KR2019900001233 U KR 2019900001233U KR 900001233 U KR900001233 U KR 900001233U KR 920001490 Y1 KR920001490 Y1 KR 920001490Y1
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KR
South Korea
Prior art keywords
magnet
tie
magnetic field
cloth
neck
Prior art date
Application number
KR2019900001233U
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English (en)
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KR910014947U (ko
Inventor
김효성
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김효성
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Priority to KR2019900001233U priority Critical patent/KR920001490Y1/ko
Publication of KR910014947U publication Critical patent/KR910014947U/ko
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Publication of KR920001490Y1 publication Critical patent/KR920001490Y1/ko

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069I/O lines read out arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096Write circuits, e.g. I/O line write drivers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Abstract

내용 없음.

Description

자석이 내장된 넥타이
제 1 도는 본 고안의 분리사시도.
제 2 도는 본 고안의 요부 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 넥타이 2 : 라벨천
3 : 자석 4 : 보호천
본 고안은 넥타이를 메고 생활하는 사람들에게 자기를 공급키 위한 자석이 내설된 넥타이에 관한 것이다.
주지하는 바와같이 자장내에 전기적도체가 유동하면 그 도체가 기전력이 유기되는 것으로서 그 기전력의 세기는 자장의 세기와 도체의 운동속도에 비례하는 것이다.
지구는 남북에 극을 가진 하나의 큰 자석으로서 지표면은 지구자석의 자장내에 있는 것으로서 지표면을 달리는 무수한 동물체에는 미세하지만 달리는 속도에 따른 기전력이 유기되고 이와같은 기전력은 마찬가지로 인체에 좋은 영향을 미침이 경험칙에서 입증되고 최근 많은 연구 논문에서 발표되곤 하였던 것이다. (혹자는 동일 이론으로 이를 자기가 인체에 유익한 효과가 있다고도 설시함) 현금에 이르러 인간은 활동시간이 줄어들고 특히 도시인은 더욱 활동시간이 줄어듬과 동시 생활공간이 자장과 차폐하는 철근조 건물에서 생활하므로서 지구자장의 영향이 극도로 감소하게 되어 자장의 유익으로부터 배제되므로서 이로인한 질병에 노출되고 있는 것이다.
이와같은 피해를 극복하기 위한 방법으로 자석이 내장된 벨트, 신발창, 셔어츠 등이 안출된바 있으나 이들은 모두 인체에 부착하여 사용하므로 결국 인체와 같이 움직이게 되어 자장의 효과가 반감되기 쉬운 것이었다.
본 고안은 이러한 결점을 해소키 위한 것으로서 넥타이(1) 이면에 라벨천(2)이 붙은 것에 있어터 라벨천(2) 이면에 자석(3)을 안치하여 자석(3)이 이탈되지 아니하도록 보호천(4)로 봉착시킨 것이다.
이와같이 된 본 고안의 작용효과를 설명하면 통상의 넥타이(1)을 매게 되면 라벨천(2)는 보통 인체의 심장부위에 있게 되므로 라벨천(2) 이면에 내장된 자석(3)의 자장은 심장부위에 강한 자장을 형성하게 된다. 그러므로 심장은 개인적 차이는 있으나 강하게 혈액을 순환시키므로 혈액은 결국 자장내에서 유통하게 되어 본원고안의 타넥타이(1)을 착용하고 있는 한 인체는 활동의 유무에 관계없이 정도의 차이는 있으나 혈액에 자장의 효과가 미치게 되는 것이다.
그러므로 본원고안은 활동이 적어진 현대인 및 자장으로부터 차폐되고 있는 도시 생활인에게 모자라는 자장의 효력을 극히 간편한 구조로서 가장 효과적으로 제공할 수 있는 것으로 손쉽고 간편하게 이용될 수 있는 것이며 라벨천(2) 하단에 내장된 자석(3)의 세기를 표시할 수 있음으로 이용자가 자신에게 알맞는 자석이 내장된 넥타이(1)를 착용할 수 있어 매우 유익하게 널리 이용될 수 있게 되는 것이다.

Claims (1)

  1. 넥타이(1) 이면에 라벨천(2)이 붙은 것에 있어서 라벨천(2) 이면에 자석(3)을 안치하여 자석(3)이 이탈되지 아니하도록 보호천(4)로 봉착시킨 자석이 내장된 넥타이.
KR2019900001233U 1990-02-03 1990-02-03 자석이 내장된 넥타이 KR920001490Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900001233U KR920001490Y1 (ko) 1990-02-03 1990-02-03 자석이 내장된 넥타이

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900001233U KR920001490Y1 (ko) 1990-02-03 1990-02-03 자석이 내장된 넥타이

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KR910014947U KR910014947U (ko) 1991-09-25
KR920001490Y1 true KR920001490Y1 (ko) 1992-03-05

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