KR920001331B1 - Semiconductor memory device - Google Patents

Abstract

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Description

Semiconductor memory device

1 is a circuit diagram showing the configuration of a bit-sensing amplifier section of a DRAM according to an embodiment of the present invention.

2 is a circuit diagram showing the overall configuration of the DRAM shown in FIG.

3 is a circuit diagram showing a memory cell configuration of the DRAM shown in FIG.

4 is a circuit diagram showing the configuration of the CMOS flip-flop shown in FIG.

FIG. 5 is a circuit diagram showing the configuration of the write input circuit shown in FIG.

6 is a circuit diagram showing a load circuit configuration of the BICMOS differential amplifier shown in FIG.

7 illustrates operation timing of a DRAM according to the present invention.

8 to 10 are circuit diagrams showing the configuration of a bit line amplifier amplifier according to another embodiment of the present invention.

11 is a circuit diagram showing the configuration of a conventional bit line sense amplifier.

* Explanation of symbols for main parts of the drawings

1: DRAM cell 2: CMOS flip-flop

3: input circuit 5: BICMOS differential amplifier (second differential amplifier)

6,17: load circuit 41,42: CMOS differential amplifier (first differential amplifier)

: 비트선B1, B2: output node BL,

: Bit line

: 입력데이터선 OL,

: 출력데이터선IL,

: Input data line OL,

: Output data line

Q1 ~ Q4: Driving MOS Transistor

Q5 ~ Q8: MOS transistor for load

Q9, Q10: MOS transistor for current source

Q11 ~ Q14, Q81 ~ Q84: MOS transistor for switching

Q15: MOS transistor for activation

Q43, Q44: MOS transistor for precharge

Q45: MOS transistor for equalizer

WL: word line

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which achieves high speed and high integration by using a bit line sense amplifier in which a MOS transistor and a bipolar transistor are combined.

[Traditional Technology and Problems]

The integration degree of the dynamic random access memory (hereinafter referred to as DRAM) is increasing as micromachining technology is advanced, and the access time of DRAM is getting shorter and shorter due to the improved reliability of the device by miniaturization. However, in the future, when the gate length of the MOS transistor is about 0.5UM or less, the power supply voltage must be lowered to secure the reliability of the device. Accordingly, a method of increasing the speed by introducing a bipolar transistor having a larger current driving capability than the MOS transistor has been proposed. For example, a differential in which a bipolar transistor is used as a driver for a bit access amplifier is combined with a MOS transistor. A method using an amplifier has been proposed.

As described above, a circuit configuration in which a bipolar transistor and a MOS transistor are combined is referred to as a BIMOS circuit, and in particular, a circuit in which a CMOS circuit and a bipolar transistor are combined is referred to as a BIMOS circuit. In this case, only a MOS transistor is a sense amplifier. As a result, the area is larger than that of a pair of bit line pairs, and a method of installing a set of BIMOS sense amplifiers in a plurality of bit line pairs has been proposed (in Japanese Patent Laid-Open No. 61-142594 and Japanese Patent Laid-Open No. 61-170992). .

However, since the memory cell of the CRAM has a destructive read type composed of one transistor and one capacitor, the information is erased once the information is read out. Rewriting is necessary. For this reason, conventionally, a CMOS flip-flop is used as a bit line sense amplifier, whereby rewriting is performed simultaneously with information detection of a memory.

On the other hand, in order to read the information of the memory cell at high speed, it is preferable to operate the BICMOS differential amplifier before operating the CMOS flip-flop. However, when the bit line is directly connected to the base of a transistor used for driving in the BICMOS differential amplifier, the signal charge of the memory cell transferred to the bit line flows to the base current, thereby erasing the information of the memory cell. Therefore, it is proposed to provide a buffer circuit with high input impedance between the BICMOS differential amplifier and the bit line.

)에 각각 접속되고, CMOS 증폭기(42)의 구동용 MOS 트랜지스터(Q3,Q4)의 게이트는 다른 비트선쌍(BL1,

)에 각각 접속되며, 이들 CMOS 차동증폭기(41,42)의 출력노드(B1,B2)는 공통의 BICOMS 차동증폭기(5)의 입력단자인 바이플러트랜지스터(T1,T2)의 베이스 접속되어 있다. 또한, CMOS 차동증폭기(41,42)는 활성화용 MOS 트랜지스터(Q9,Q10)의 게이트가 열선택용 클록(CSL1,CSL2)에 의해 선택적으로 구동되게 됨으로써 어느 한쪽이 선택되도록 되어 있다.FIG. 11 is a circuit diagram showing an example of a conventional BICMOS sense amplifier. The sense amplifier is a buffer amplifier provided for each bit line pair and includes a CMOS differential amplifiers 41 and 42 and a BICMOS differential amplifier 5 using a bipolar transistor. Consists of. Wherein the CMOS differential amplifiers 41 and 42 are P-channel MOS transistors [Q5, Q6]. (Q7, Q8)] as a current mirror type CMOS differential amplifier as a load, and as a CMOS differential amplifier, the gates of the driving MOS transistors Q1 and Q2 of the CMOS amplifier 41 are connected to the bit line pair BL0,

Are connected to the respective gate lines of the driving MOS transistors Q3 and Q4 of the CMOS amplifier 42, respectively.

The output nodes B1 and B2 of these CMOS differential amplifiers 41 and 42 are respectively connected to the bases of the bi-flush transistors T1 and T2 which are input terminals of the common BICOMS differential amplifier 5, respectively. In the CMOS differential amplifiers 41 and 42, the gates of the MOS transistors Q9 and Q10 for activation are selectively driven by the column selection clocks CSL1 and CSL2 so that either one of them is selected.

),(BL1,

)]중 BL0와

가 선택된 경우를 고려해 보면, 이때 선택되지 않은 비트선쌍(BL1,

)층의 CMOS 차동증폭기(42)에서 구동용 MOS 트랜지스터(Q3,Q4)는 그 공통소오스가 부유상태(플로우팅상태)로 되기 때문에 (BL1,

)의 “H”,“L”가 명확히 결정되기 까지는 모두 온상태로 되게 된다. 따라서 출력노드(B1,B2)간에 상기 MOS 트랜지스터(Q3,Q4)를 통해서 고저항의 직류통로가 형성되게 되어 이들이 데이터간섭의 원인으로 되게 됨으로써 충분한 센스감도가 얻어지지 않게 된다. 또, 출력노드(B1,B2)는 선택되지 않은 비트선(BL1,

)측의 CMOS 차동증폭기(42)의 구동용 MOS 트랜지스터(Q3,Q4)를 통해서 비트선(BL1,

)과 용량결합되기 때문에 출력데이터에 잡음이 입력되게 됨으로써 이것도 센스감도 저하의 원인으로 되게 된다.In the case of using the BICMOS sense amplifier, there is a problem that data interference occurs because two buffer CMOS differential amplifiers are used together with one BICOPMS differential amplifier. That is, for example, the column selection clock is CLS1 = "H", CLS2 = "L", and 2 and the bit line pair [BL0,

), (BL1,

)] With BL0

Considering the case where is selected, the unselected bit line pair BL1,

In the CMOS differential amplifier 42 of the () layer, the driving MOS transistors Q3 and Q4 have the common source in a floating state (floating state) (BL1,

) Will remain on until the “H” and “L” are clearly determined. Therefore, a high resistance direct current path is formed between the output nodes B1 and B2 through the MOS transistors Q3 and Q4, so that they become a cause of data interference, so that sufficient sense sensitivity is not obtained. The output nodes B1 and B2 are not selected bit lines BL1 and B1.

Bit line BL1, through the MOS transistors Q3 and Q4 for driving the CMOS differential amplifier 42 on the "

Because of the capacitive coupling, the noise is input to the output data, which also causes a decrease in the sense sensitivity.

As described above, in a BICMOS sense amplifier configured to share a BICMOS differential amplifier for a plurality of pairs of bit lines, data interference and noise mixing occur in the CMOS amplifier portion as a buffer circuit. There is a problem that the performance of the DRAM is reduced by being unable to do so.

[Purpose of invention]

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a DRAM in which the above problem is solved and its performance is improved.

[Configuration of Invention]

In order to achieve the above object, the present invention provides a BVICOMS differential amplifier based on a CMOS differential amplifier (first differential amplifier) as a buffer circuit and a BICPMS differential amplifier (second differential amplifier) connected to an output node of the first differential amplifier. A CRAM having a bit-sensing amplifier configured to be provided for each CMOS differential amplifier, wherein the switching MOS transistor is controlled by a clock between the driving MOS transistor and the output node of the CNOS differential amplifier. It is.

[Action]

According to the above configuration, the switching MOS transistor of the CMOS differential amplifier is turned off with respect to the unselected bit line pairs, thereby eliminating data interference between the output nodes of the CMOS differential amplifier, and the presence of the switching MOS transistor. As a result, the capacitive coupling between the output node and the bit line of the CMOS differential amplifier is reduced, thereby suppressing noise mixing.

EXAMPLE

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

: (BL0,

),(BL1,

),...] 및 메모리셀(1)을 선택 구동시키기 위한 복수개의 워드선(WL : WL0,WL1,....)이 배설되어 있고, 각 비트선쌍(BL,

)에는 정보독출 및 기록시에 액티브 리스토어(active restore)를 수행하기 위한 CMOS 플립플롭(2)이 설치되어 있는데, 여기서 상기 CMOS 플립플롭(2)은 제4도에 도시된 바와 같이 2개의 P챈널 MOS 트랜지스터(Q21,Q22)와 2개의 N챈널 MOS 트랜지스터(Q23,Q24)로 구성된 공지의 것이다. 또 각 비트선쌍(BL,

)과 입력데이터선(IL,

)과의 사이에는 기록용의 입력회로(3)가 설치되어 있는데, 이 입력회로(3)는 예컨대 제5도에 도시된 바와 같이 열선택클록(øA)이 입력되는 트랜스퍼게이트용(TRANSFER GATE 用) N챈널 MOS 트랜지스터(Q31,Q32)와 기록클록(øw)이 입력되는 트랜스퍼게이트용 N챈널 MOS 트랜지스터(Q33,Q34)로 구성되어 있다.FIG. 2 shows the overall configuration of a DRAM according to an embodiment of the present invention. In FIG. 2, reference numeral 1 denotes a DRAM cell (or a dummy cell), and this DRAM cell is shown in FIG. It consists of one MOS transistor QM and one capacitor CM. Such DRAM cells are arranged in a matrix on a semiconductor substrate to form a memory cell array. In addition, for the memory cell array, a plurality of pairs of bit lines BL to transmit and receive information charges to and from each memory cell 1 are provided.

: (BL0,

), (BL1,

), ...] and a plurality of word lines (WL: WL0, WL1, ...) for selectively driving the memory cells 1, and each bit line pair BL,

) Is provided with a CMOS flip-flop 2 for performing an active restore during information reading and writing, wherein the CMOS flip-flop 2 has two P-channels as shown in FIG. It is a known one composed of MOS transistors Q21 and Q22 and two N-channel MOS transistors Q23 and Q24. Each bit line pair (BL,

) And input data line (IL,

There is provided an input circuit 3 for recording, which is used for the transfer gate to which the column select clock øA is input, for example, as shown in FIG. ) N-channel MOS transistors Q31 and Q32 and transfer gate N-channel MOS transistors Q33 and Q34 to which the write clock? W is input.

)에 직접 접속된 제1차동증폭기인 CMOS 차동증폭기(41,42)와, 이 CMOS 차동증폭기(41,42)의 출력노드에 접속된 제2차동증폭기인 BICMOS 차동증폭기(5)로 구성되어 있는데, 그 구체적인 구성예는 제1도에 도시되어 있다. 즉 제1도에서 CMOS 차동증폭기(41,42)는 구동용 N챈널 MOS 트랜지스터(Q1,Q2,Q3,Q4)와 전류원용 N챈널 MOS 트랜지스터(Q9,Q10) 및, 전류미러형 부하를 구성해 주는 P챈널 MOS 트랜지스터(Q5,Q6,Q7,Q8)를 기본으로 해서 구성되어 있는데, 여기서 상기 구동용 MOS 트랜지스터(Q1,Q2)와 부하용 MOS 트랜지스터(Q5,Q6)의 사이에는 스위칭용 N챈널 MOS 트랜지스터(Q11,Q12)가 설치되고, 마찬가지로 상기 구동용 MOS 트랜지스터(Q3,Q4)와 부하용 MOS 트랜지스터(Q7,Q8)의 사이에는 스위치용 N챈널 MOS 트랜지스터(Q13,Q14)가 설치되며, 상기 전류원용 MOS 트랜지스터(Q9,Q10)의 게이트에는 (1/2)V_CC이하의 중간전위(VM)가 인가되고 있다. 또한 도면에서 알 수 있는 바와 같이 이 들 CMOS 차동증폭기(41,42)에 있어서는 2쌍의 비트선에 대해서 1쌍의 출력노드(B1,B2)가 설치되어 있고, BICMOS 차동증폭기(5)는 컬렉터가 각각 출력데이터선(OL,

)에 접속됨과 더불어 에미터가 공통접속된 구동용으로서의 NPN 트랜지스터(T1,T2)와 활성화용 N챈널 MOS 트랜지스터(Q15)로 구성되어 있으며, 상기 CMOS 차동증폭기(41,42)의 2개의 출력노드(B1,B2)가 각각 상기 NPN 트랜지스터(T1,T2)의 베이스 접속되어 있다.The bit line sense amplifiers have a bit line pair (BL,

CMOS differential amplifiers 41 and 42, which are directly connected to the first differential amplifier, and BICMOS differential amplifiers 5, which are second differential amplifiers connected to the output nodes of the CMOS differential amplifiers 41 and 42. The specific configuration example is shown in FIG. That is, in FIG. 1, the CMOS differential amplifiers 41 and 42 constitute N driving CHANNEL MOS transistors Q1, Q2, Q3 and Q4, N channel MOS transistors Q9 and Q10 for current source, and a current mirror type load. The main circuit is configured based on the P-channel MOS transistors Q5, Q6, Q7, and Q8, wherein the switching N-channel is between the driving MOS transistors Q1 and Q2 and the load MOS transistors Q5 and Q6. MOS transistors Q11 and Q12 are provided, and similarly, switching N-channel MOS transistors Q13 and Q14 are provided between the driving MOS transistors Q3 and Q4 and the load MOS transistors Q7 and Q8. An intermediate potential (VM) equal to or less than (1/2) V _CC is applied to the gates of the current source MOS transistors Q9 and Q10. As can be seen from the figure, in these CMOS differential amplifiers 41 and 42, one pair of output nodes B1 and B2 are provided for two pairs of bit lines, and the BICMOS differential amplifier 5 is a collector. Are the output data lines (OL,

) And NPN transistors (T1, T2) for activation and N-channel MOS transistors for activation (Q15), which are connected to the emitter and are commonly connected, and two output nodes of the CMOS differential amplifiers (41, 42). (B1, B2) are connected to the base of the NPN transistors T1, T2, respectively.

As described above, the share of the CMOS differential amplifiers 41 and 42 is shared by two pairs of bit lines, and the BICMOS differential amplifier 5 is shared by two pairs of bit lines, thereby occupying an area larger than that of the MOS transistors. It is possible to suppress an increase in the pattern area by using a large transistor. In this case, the activation MOS transistor Q15 is controlled by a clock ø.

)에는 복수의 BICMOS 차동증폭기(5)에 대해 공통인 부하회로(6)가 설치되어 있는데, 이 부하회로(6)는 예컨대 제6도에 도시된 바와 같이 다이오드 접속된 NPN 트랜지스터(T3,T4)와, 이들과 병렬접속된 P챈널 MOS 트랜지스터(Q41,Q42)를 기본으로 해서 구성된 것으로, 여기서 상기 NPN 트랜지스터(T3,T4)는 출력데이터선(OL,

)에 대해서 고속충전을 하기 위한 부하이고, 이 NPN 트랜지스터(T3,T4)와 병렬접속된 상기 P챈널 MOS 트랜지스터(41,42)는 NPN 트랜지스터(T3,T4)에 의한 VRE의 전압강하에 따르지 않고 출력데이터선(OL,

)의 “H”레벨전위가 Vcc까지 되도록 해주기 위한 것이다.Meanwhile, as shown in FIG. 2, the output data lines OL,

) Is provided with a common load circuit 6 for a plurality of BICMOS differential amplifiers 5, which are diode connected NPN transistors T3 and T4, for example, as shown in FIG. And the P-channel MOS transistors Q41 and Q42 connected in parallel therewith, wherein the NPN transistors T3 and T4 are output data lines OL,.

The P-channel MOS transistors 41 and 42 connected in parallel with the NPN transistors T3 and T4 are not subjected to the voltage drop of the VRE by the NPN transistors T3 and T4. Output data line (OL,

) To make the “H” level potential up to Vcc.

)을 V_CC전위로 설정하기 위한 프리차지(precharge)용 P챈널 MOS 트랜지스터(Q43,Q44) 및 이퀄라이저로서의 P챈널 MOS 트랜지스터(Q45)를 갖추고 있는데, 이들 MOS 트랜지스터(Q43~Q45)는 클록(øEGL)에 의해 제어되게 된다.The load circuit 6 also has other output data lines OL,

P channel MOS transistors (Q43, Q44) for precharge and P channel MOS transistors (Q45) as equalizers for setting V to the V _CC potential. These MOS transistors (Q43 to Q45) are clocks (øEGL). Will be controlled by

Hereinafter, the operation of the DRAM configured as described above will be described with reference to FIG.

)에 나타나게 된다. 이어 열어드레스에 의해 선택된 입력회로(3)가 구동되어 입력데이터선(IL,

)으로부터 기입대상으로 되는 정보가 입력되게 되고, 그후 CMOS 플립플롭(2)의 전원클록(øSAN,øSAP)이 인가되어 CMOS 플립플롭(2)이 동작하게 됨으로써 메모리셀(1)로의 정보기입이 실행되게 된다.First, the information writing operation is as follows. In other words, when the word line WL selected by the row address is driven, the information of the memory cell 1 selected by this is precharged to Vcc, for example (1/2).

Will appear. Then, the input circuit 3 selected by the open dress is driven to input data lines IL,

Information to be written into is inputted, and then the power supply clocks (øSAN, øSAP) of the CMOS flip-flop 2 are applied, and the CMOS flip-flop 2 is operated so that information writing to the memory cell 1 is executed. Will be.

Next, the read operation will be described.

)에 나타나게 되는데, 이때 열선택신호선이 CLS1=“H”, CSL2=“L”인 경우를 고려해 보면, 비트선(BL0,

)측의 CMOS 차동증폭기(41)는 증폭기로서 동작하고, 비트선(BL1,

)측의 CMOS 차동증폭기(42)는 스위칭용 MOS 트랜지스터(Q13,Q14)가 오프이기 때문에 동작하지 않게 됨으로써 비트선(BL0,

)의 정보가 출력노드(B1,B2)로 독출되게 된다. 이어 클록(ø)에 의해 활성화된 BICMOS 차동증폭기(5)에 의해 이 출력노드(B1,B2)의 정보가 출력선(OL,

)으로 독출되게 되는데, 이때 선택되지 않은 CMOS 차동증폭기(42)는 구동용 MOS 트랜지스터(Q3,Q4)가 동시에 온되는 경우가 있어도 스위치용 MOS 트랜지스터(Q13,Q14)에 의해 그 2개의 출력노드사이드는 완전히 절단되게 된다. 이에따라, 출력노드(B1,B2)간의 데이터간섭은 발생되지 않게 되고, 또 스위칭용 MOS 트랜지스터(Q13,Q14)의 존재에 의해 구동용 MOS 트랜지스터(Q3,Q4)의 게이트와 출력노드(B1,B2)간의 기생용량이 매우 작아지게 되어 노이즈혼입도 적게 된다.At the time of reading information, the selected word line WL is activated so that information of the memory cell is changed to

In this case, considering that the column selection signal line is CLS1 = “H” and CSL2 = “L”, the bit line BL0,

CMOS differential amplifier 41 on the side of "

CMOS differential amplifier 42 on the side of < RTI ID = 0.0 > 1 < / RTI >

) Information is read out to the output nodes B1 and B2. Subsequently, the information of these output nodes B1 and B2 is supplied by the BICMOS differential amplifier 5 activated by the clock ø.

In this case, the unselected CMOS differential amplifiers 42 are connected to the two output node sides by the switching MOS transistors Q13 and Q14 even when the driving MOS transistors Q3 and Q4 are simultaneously turned on. Will be cut completely. Accordingly, no data interference occurs between the output nodes B1 and B2, and the gates of the driving MOS transistors Q3 and Q4 and the output nodes B1 and B2 are prevented due to the presence of the switching MOS transistors Q13 and Q14. Parasitic capacitance is very small, resulting in less noise mixing.

Next, the signals 1oSAN and 1oSAP for activating the CMOS flip-flop 2 are sequentially input so that an active restore is performed.

As described above, according to the embodiment of the present invention, by amplifying the CMOS differential amplifier for the buffer of the BICMOS sense amplifier, mutual interference of the read data is prevented, and data is erroneously read by the data of the unselected bit line. Will be prevented.

FIG. 8 illustrates a configuration of a bit sense amplifier unit according to another embodiment of the present invention, in which a part corresponding to FIG. 1 is denoted by the same reference numeral as in FIG. 1, and a detailed description thereof is omitted.

In the embodiment shown in FIG. 8, the resistors R1 to R4 are used as the loads of the CMOS differential amplifiers 41 and 42, and the resistors R5 and R6 are similarly used as the loads of the BICMOS differential amplifiers 5, respectively. In this way, the same effects as in the first embodiment can be obtained by this embodiment as well.

FIG. 9 is a circuit diagram showing the configuration of a bit sense amplifier according to another embodiment of the present invention, in which portions corresponding to those of FIG. 1 are denoted by the same reference numerals as those of FIG.

In the present embodiment shown in FIG. 9, a common load circuit 17 is provided as a load of the CMOPS differential amplifiers 41 and 42, which are the first differential amplifiers, where the load circuits 17 form a pair P. FIG. Although it is a current mirror type load composed of channel MOS transistors Q71 and Q72, it should be configured using a resistor as shown in FIG. 8 instead of P channel MOS transistors Q71 and Q72. By using it, the number of parts can be reduced.

FIG. 10 is a circuit diagram illustrating a configuration of a bit sense amplifier unit according to another embodiment of the present invention. In FIG. 10, parts corresponding to those of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the embodiment shown in FIG. 10, a pair of N-channel switching MOSs operated by the clock signal CSL1 between the CMOS differential amplifiers 41 and 42, which are the first differential amplifier, and the second differential amplifier 5, are used. The transistors Q81 and Q82 and a pair of N-channel switching MOS transistors Q83 and Q84 operated by the clock signal CSL2 are inserted into each other. It becomes possible.

The present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit thereof.

[Effects of the Invention]

As described above, according to the present invention, a switching MOS transistor controlled by a clock is provided between a driving MOS transistor of a first differential amplifier used as a buffer in a BICMOS sense amplifier and a load, so that the bit line is unselected. By turning off the switching MOS transistor, it is possible to realize a DRAM in which data interference and noise are prevented from being prevented and operation reliability can be improved.

Claims (6)

A plurality of memory cells 1 arranged in a matrix on a semiconductor substrate, and a plurality of pairs of bit lines BL for carrying a signal charge line with each of the memory cells 10;

: (BL0,

), (BL1,

..., a plurality of word lines (WL; WL0, WL1, ...) arranged to intersect these bit line pairs (BL, BL) to select a memory cell, and each of the bit line pairs (BL,

) And paired bit lines BL,

Are respectively connected to first differential amplifiers 41 and 42 composed of MOS transistors each having an input node connected thereto, and output nodes B1 and B2 constituting a pair of the first differential amplifiers 41 and 42 respectively. In a semiconductor memory device in which a sense amplifier including a second type amplifier 5 using bipolar transistors T1 and T2 for driving is integrated, the second differential amplifier 5 is the first differential amplifier. One for each of the plurality of (41,42) is provided, and the clock CSL1 is provided between the driving MOS transistors Q1 to Q4 of the first differential amplifiers 41 and 42 and the second differential amplifier 5. And a switching means controlled by the CSL2. The method of claim 1, wherein each of the second differential amplifiers 41 and 42 includes a pair of driving MOS transistors Q1 to Q40 and loads Q5 to Q8, and the first differential amplifiers 41 and 42. And a switching MOS transistor (Q11 to Q14) as a switching means between the driving MOS transistors (Q1 to Q4) and the loads (Q5 to Q8) of the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the load of the first differential amplifiers (41, 42) is composed of resistance loads (R1 to R4). The semiconductor memory device according to claim 1, wherein a common load (17) is provided in the plurality of first differential amplifiers (41, 42). 2. The memory cell (1) according to claim 1, wherein the memory cell (1) comprises a MOS transistor (QM) and one capacitor (CM), and a CMOS flip-flop (2) for active restoration is connected to the bit line pairs (BL, BL). A semiconductor memory device, characterized in that. 2. The semiconductor memory device according to claim 1, wherein switching MOS transistors (Q81 to Q84) are interposed between the first differential amplifier (41, 42) and the second differential amplifier (5).

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