KR920001053Y1 - For vtr variable low-speed mode phase control circuit of capstan motor - Google Patents

Abstract

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Description

VTI's Phase Control Circuit of Capstan Motor in Variable Low-Speed Mode

1 is a circuit diagram of the subject innovation.

2 is a waveform diagram of voltages in FIG. 1.

* Explanation of symbols for the main parts of the drawings

1: Head switching pulse input terminal 2: Low speed selection signal input terminal

3: low speed setting part 4: trapezoidal waveform shaping part

5: control signal input terminal 6: switching IC

7: DC drive unit 8: motor speed control signal input terminal

9: Comparator 10: Error voltage amplifier

12: sampling / holder part R1-R8: resistance

VR: Variable resistor C1-C9: Capacitor

D1-D5: Diode Q1-Q5: Transistor

FT: Field Effect Transistor

The present invention relates to a phase control circuit of a capstan motor in a variable low speed mode of a VTIAL, in particular VT employing a digital image processing circuit.

In the conventional step-drive type variable low speed circuit, the configuration thereof is complicated and screen shake occurs when the low speed is selected, while in the case of the linear variable low speed circuit, noise flows to the screen, thereby reducing the safety of the circuit.

An object of the present invention is to solve such a closed end, and in VTI employing a digital image processing circuit, a phase of a capstan motor that enables variable low speed of two or more stages with fast response characteristics using a head switching pulse. To provide a control circuit.

In order to achieve the above object, the phase control circuit of the present invention divides the head switching pulse for the low speed setting of two or more stages, and in each of the low speed modes according to the switching by the control pulse in the state in which the divided pulse is shaped into a trapezoidal pulse. The DC level of the corresponding trapezoidal pulse is sampled and honed, and the capstan motor voltage is applied to the capstan motor by applying the capstan error voltage which is compared with the speed control signal of the capstan motor frequency generator after direct-current driving the sampled / horned output. It is configured to control the low speed mode.

Hereinafter, the specific configuration and effect of the present invention will be described in detail by the accompanying drawings.

1 is an implementation circuit diagram of the present invention, in which a monostable multivibrator MM1 and a output of the monostable multivibrator MM1 whose head switching pulses are input and whose time constants are varied in two steps by a low speed selection logic signal are shown. Take out from the low speed setting part 3 which consists of a monostable multivibrator for cycle conversion (MM2), the trapezoidal waveform shaping part 4 which shape | shapes the output of this low speed setting part 3 to the signal inverted trapezoidal wave form, and a reproduction tape. Sampling / holder section 12 of switch IC 6 for differentiating the control pulse to be controlled and switching the output of the trapezoidal waveform shaping section 4 by controlling the peak value of the differential waveform, and the sampling / calling A direct current driver 7 including a field effect transistor FT for driving the output of the wool part 12, and a speed control obtained by outputting the output of the direct current driver 7 from a conventional capstan motor driving frequency generating circuit; signal Comparing the comparator 9, and amplifies the output of the error voltage of the comparator (9) signal consists of a voltage error amplifying section 10 to a conventional capstan gwehan Motor that.

In the embodiment of the present invention, the capacitor C1 and the resistor R3 and R4 connected to the correction means T1 and T2 of the monostable multivibrator MM1 in the low speed setting section 3 are set. The time constant is varied by the transistor Q1 which is switched and controlled by the low speed selection logic signal, and the low speed fine adjustment variable resistor VR is provided to the correcting means T1 (T2) of the monostable multivibrator MM2 for duty cycle conversion. Is connected to the transistor Q2 and the time constant circuit of the capacitor C2 and the resistor R7.

In addition, the trapezoidal waveform shaping portion 4 of the present invention includes a coupling capacitor (C3) and a switching transistor (Q3) (Q4), charge and discharge capacitor (C4) (C5), diode (D1) and for adjusting the inclination angle of the trapezoidal waveform It consists of resistors R8-R11.

1 is the head switching pulse input terminal, 2 is the low speed selection signal input terminal, 5 is the control signal input terminal, 8 is the motor speed control signal input terminal, 11 is the error voltage output terminal, B + is the DC power supply, R1 R2, R5, R6, R12-R18 are resistors, C6-C9 are capacitors, D2-D5 are diodes, Q5 are transistors.

The digital image processing method VTI's capstan motor phase control circuit pulse-modulates the control pulse taken out from the tape during normal playback mode, and controls the phase of the capstan motor by the modulation waveform. Phase control is difficult with only the control signal.

In the present invention, the head switching pulse having the form of FIG. 2 (a) is input through the terminal 1 and applied to the monostable multivibrator MM1 in the low speed setting section 3.

In addition, the low speed selection logic signal input through the terminal 2 is a logic signal which becomes a high or low level according to a selection speed selected by a user, and the switching transistor Q1 is turned on by this logic signal. By turning on or off, the resistor R3 (R4) is selectively connected to the correcting means T1 (T2) of the monostable multivibrator MM1 to convert the time constant of the monostable multivibrator MM1. . Therefore, the constants of the time constants of the capacitor C1 and the resistors R3 and R4 are adjusted, and the head is passed through the output terminal of the monostable multivibrator MM1 as shown in FIG. 2 (b) (c). Output pulses corresponding to the selected switching pulses (1 / N) (1 / 2N), that is, pulses having different set time (t1) (t2) are outputted, and these pulses are output by the low speed selection logic signal. One of the pulses will be selected.

Such a waveform is prepared by the monostable multivibrator MM2 as a preparation waveform for forming a trap waveform as shown in FIG. 2 (d), and its duty cycle is changed and input to the trapezoidal waveform shaping section 4, whereby Through the trapezoidal waveform shaping unit 4, a pulse of the phase inverted trapezoidal waveform is obtained as shown in FIG. In this case, the variable resistor VR1 connected to the monostable multivibrator MM2 is used to finely adjust the duty cycle of the waveform of FIG. 2d in the low speed mode, and the duty cycle of the waveform is the capacitor C2. Is set by the resistor R7 and the variable resistor VR, and the waveform is unintegrated and integrated by the transistor Q3, the capacitor C4 and the resistor R10 in the trapezoidal waveform shaping section 4, and the transistor Q4. By driving), it becomes a trapezoidal waveform as shown in FIG.

Meanwhile, in the embodiment of the present invention, the low speed setting unit 3 is configured to have two low speed modes. However, the low speed setting unit 3 has a low speed mode of three or more steps by a combination of time constant circuits using a low speed selection signal according to the three or more low speed modes. It becomes possible.

The trapezoidal pulse output from the trapezoidal waveform shaping section 4 is applied to the switch IC 6 in the sampling / holder section 12. At this time, the control pulse is taken out from the regeneration tape and input through the terminal 5. The switch IC 6 is switched by the differential waveform peak value (waveform in FIG. 2 (f)) which has passed through the differential circuit of the capacitor D6 and the resistor R12 in the sampling / holder portion 12. . Therefore, the DC level point corresponding to the selected low-speed mode among the inclined portions a of the trapezoidal pearl number applied to the switching 6 is sampled / holed, and then output to the DC driver 7.

The sampling / holder output input to the DC driver 7 is driven by the capacitor C7 and the field effect transistor FT to form a waveform Ve as shown in FIG. Enter it.

Thus, the waveform voltage input to the comparator 9 is compared with the speed control signal taken out from the frequency generating circuit of the capstan motor, which is input via the terminal 8, so that the comparator 9 An error voltage is output. The error voltage is voltage-driven by the transistor Q5 in the error voltage amplifier 10, and then supplied to the error signal input terminal of the capstan motor to control the phase of the capstan motor.

As described above, the present invention has a merit in that VTI having a digital image processing circuit has two-stage low-speed mode without generating screen shake or screen noise since precise phase control of the capstan motor is performed by using a head switching pulse. There is this.

Claims (2)

A monostable multivibrator MM1 whose head switching pulse is an input signal and whose time constant is varied by a low speed selection logic signal and a monostable multivibrator MM2 for duty cycle conversion of the output of the monostable multivibrator MM1 The low speed setting section 3, the trapezoidal waveform shaping section 4 for shaping the output of the low speed setting section 3 into a trapezoidal waveform inverted signal, and the control pulses taken out from the reproduction tape, A sampling / holder portion 12 of a switching IC 6 which is controlled by a peak value and switches the output of the trapezoidal waveform shaping portion 4, and voltage-drives the output of the sampling / holder portion 12. The DC drive unit 7 including the field effect transistor FT and the capacitor C7, and the output of the DC drive unit 7 are compared with the speed control signal taken out from a conventional capstan motor driving frequency generation circuit. Of A comparator 9 for outputting a differential voltage, and an error voltage amplifier 10 for amplifying the eddy voltage, which is the output of the comparator 9, and returning it to the error signal input terminal of a conventional capstan motor. VT's variable low-speed mode capstan motor phase control circuit. A time constant setting capacitor (C1) and a resistor (R3) (R4) according to claim 1, wherein the low speed setting section (3) is connected to the correction means (T1) (T2) of the monostable multivibrator (MM1). And a transistor (Q1) for varying the set time constant by the capacitor (C1) and the resistors (R3) and (R4) by switching control by a low speed selection logic signal of the monostable multivibrator (MM2) for duty cycle conversion. The low speed fine adjustment variable resistor VR connected to the correction means T1 and T2, the transistor Q2 driven and controlled by the variable resistor VR, the time constant setting capacitor C2 and the resistor R7 are controlled. Phase control circuit of the variable low speed mode capstan motor of VTAL comprising a.