KR920000885B1 - Screen extension circuit - Google Patents

Abstract

The circuit magnifies a desired portion of the picture of a television by linearly compensating the video signals in the horizontal and vertical directions. The circuit includes: a control logic circuit (43) for generating data selection control signals; a frame memory (44) for storing the data; a delaying circuit (46) for delaying the output of the frame memory (44); a first adder (47) for summing up the output of the delaying circuit (46); a first half value period generator (48) for dividing the output of the first adder into two halves; two AND gates for selecting the output of the first half value period generator; an OR gate for summing up the output of the AND gates; a clock delaying circuit (50) for delaying the output of the OR gate; a second adder (51); a second half value period generator (52); other AND gates and another OR gate.

Description

Screen magnification circuit in progressive scan television system

1 is a diagram illustrating a quantized signal for storage in a memory of a conventional television screen signal.

Figure 2 is an exemplary view according to the conventional signal expansion.

3 is an exemplary screen display of the conventional screen according to the first and second degrees.

4 is a circuit diagram according to the present invention.

5 is a signal enlargement example according to the present invention.

6 is an exemplary screen display according to the present invention.

7 is a general sequential scanning television and an enlarged waveform waveform according to the present invention.

8 is an exemplary view of a screen according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a circuit for enlarging a portion of an image screen in a progressive scan type television system. In particular, the present invention relates to a progressive scan type television such as an ID (Improved Definition) TV and an Extended Defininition (ED) TV receiver. The present invention relates to a screen magnification circuit in a progressive scan television system suitable for expanding a predetermined portion by linearly interpolating a video signal in horizontal and vertical directions.

In general, a progressive scan type TV is divided into a radix field and an even field to display one frame. In the sequential scanning method, the magnification function is intended to enlarge a desired portion to a desired size. For example, the magnification function adopted by ID-TV (Model-30ID1) sold by Toshiba, Japan, is a conventional technique. The size of pixels on the screen was enlarged by increasing the size horizontally and vertically.

Briefly describing the conventional magnification method with reference to FIGS. 1-3, the complex video signal is sampled at a predetermined sampling frequency (4fsc) as shown in FIG. 1, and then quantized into predetermined bits and stored as frame-by-frame data in the frame memory as digital image data. do.

When the size of the pixel of FIG. 3a of the screen of the digital image signal stored in the frame memory is enlarged horizontally and vertically by 2 times, it is read from the frame memory and repeatedly scanned twice as horizontally and vertically as shown in FIG. The part is doubled. However, the distance between the pixels (between (a)-(b) and (a)-(f)) of the enlarged screen as shown in FIG. 2 is also doubled, so that the boundary between the pixels becomes noticeable. Accordingly, there is a problem that the screen becomes rough overall.

Accordingly, an object of the present invention is to provide a circuit for removing the roughness of an enlarged screen by removing a pixel boundary plane by using a linear interpolation method in which the average value of the two pixels is written between pixels that are horizontally and vertically stretched during the enlargement function.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram according to the present invention, which is vertical by a horizontal synchronous signal input through a horizontal signal input terminal 41 detected from a synchronous detection circuit (not shown) and a basic clock signal input to a clock terminal 42. ㆍ A control logic circuit 43 for generating a selection addressing signal of image data according to horizontal enlargement and a data selection control signal according to vertical and horizontal linear interpolation, and an image signal of even and odd fields is digitized and stored in units of frames. A frame memory 44 into which the enlarged data is read according to the address signal according to the vertical and horizontal enlargement of the control logic circuit 43, and a horizontal line 1H including the data to be enlarged output from the frame memory 44; After the delay, the data input after one horizontal line is added and divided into two (1/2) to divide the divided data and the data output from the plane memory 44 into the control logic circuit 4. 3) the linear interpolation means selected by the first control signal output from 3) to obtain an average value, and the vertical linear interpolation means outputs the output of the frame memory 44 to the 1H line delay circuit 46 and the first adder ( 47), the data selector 49, and the AND gate AN2, and the output of the 1H line delay circuit 46 is added by the first adder 47, and divided by two in the first half-life 48. It is configured to be input to the gate (AN1), the output of the control logic circuit (4e) is connected to the input terminal of the AND gate (AN1, AN2), the output of the AND gate (AN1, AN2) of the oragate (OR1) It is connected to the input terminal.

The control logic circuit after inputting the 1 clock delay value and the 2 minute value by adding the value obtained by delaying the output of the vertical linear interpolation means by one clock and the output of the vertical linear interpolation means. Horizontal interpolation means for selecting an average value by selecting the second control signal outputted from 43, and the horizontal interpolation means outputs the output of the vertical linear interpolation means by one clock delay circuit 50 and the second adder ( 51) and the output of the first clock delay circuit 50 to the second adder 51 and the AND gate AN4, and the output of the second adder 51 to the second half-life 52. 2 minutes (1/2) is connected to the input terminal of the AND gate (AN3), and the second control signal of the control logic circuit 43 is input to the other input of the AND gate (AN3, AN4). The output terminals of the AND gates AN3 and AN4 are configured to be input to the oragate OR2.

5 is a diagram illustrating signal enlargement according to the present invention, and FIG. 6 is a diagram illustrating enlarged screen according to the present invention.

7 is a timing diagram according to the present invention, where (7a) and (7b) are waveform diagrams input to the horizontal synchronization input terminal 41 and the clock terminal 42 of the control logic circuit 43, and (7c), ( 7f) are first and second control signal waveforms output from the control logic circuit 43, and 7g and 7h are final output data and horizontal synchronous signal waveforms. That is, (7a) to (7b) are operation waveform diagrams of a typical progressive scan television, and (7i) to (7o) are operation waveform diagrams according to the present invention, and (7i) and (7j) are enlarged. 7A and 7L are the first and second control signal waveform diagrams of the control logic circuit 43 according to the enlargement, and 7m is the oragate of FIG. An output waveform diagram of OR1, where 7n is an output waveform of one clock delay circuit 52, and 7o is an output waveform of Oagate OR2, which is the final output according to enlargement.

8 is a screen configuration diagram according to the present invention.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 4-8. First, the background of the present invention will be briefly described, and the sequential scanning is performed by reading the stored values in the frame memory 44 two times in turn. The present invention is to improve the vertical resolution by eliminating screen flicker by writing an average value by linear interpolation.

Therefore, a circuit for quantizing a video signal and a frame memory 44 capable of storing digital video data by quantization are used, and an enlarged circuit for enlarging and viewing a portion of a screen to be particularly viewed by using the frame memory 44. Can be configured. An example is shown in Figures 1 and 2. That is, when the (a)-(b) section and the (f)-(i) section are horizontally and vertically doubled in the screen signal as shown in FIG. 1, the screen signal as shown in FIG. (Usually, a horizontal line is sampled at 900-1100 pixels and stored in memory, but here, it is assumed that 8 points are composed of pixels.)

의 화면신호를 만들어 주고(수평선형보간), (a)화소와 (f)화소사이에ㆍ

의 화면을 만들어주는 방법을 취하는(수직선형보간)것이다.However, as shown in FIG. 2, the distance between the pixels is doubled, which makes the screen rough. In order to solve this problem, the present invention attempts to solve the problem of roughening the screen by writing an average of two pixels between two pixels which are horizontally and vertically superior in the enlarged function. That is, between (a) and (b)

To make a screen signal of (horizontal linear interpolation), between (a) pixels and (f) pixels

It's taking a way to create a screen (vertical linear interpolation).

The enlarged screen signal by this method is shown in FIG. 5, which is much closer to the original waveform than the waveform of FIG. 2, and it is difficult to distinguish the pixel boundary, thereby obtaining a smooth screen. FIG. 6 shows a function of reducing roughness of the enlarged screen by calculating each waveform in FIG. 5 as shown in Table 1 below and outputting an average value with the data displayed on the TV screen (linear interpolation).

TABLE 1

TV receivers, such as ID-TV, ED-TV, etc., which improve the quality of TV images, are configured by storing digital signals of the radix field and the superior field transmitted from a broadcasting station at the same time as digital data in the frame memory 44. In the mode, when the vertical and horizontal address signals, such as the seventh and seventh degrees, are generated in the control logic circuit 43, the pixels in the frame memory 44 are read out one by one. In this case, when the horizontal address is increased by one and the data of one line is read out, the vertical addresses are increased by one to form a screen sequentially scanned as shown in FIG. 8A. At this time, the outputs of the first and second control signal stages D and E of the control logic circuit 43 are set to " high " as shown in FIG. 5 (7e) and 7f, so that the first and second half-life 48 of FIG. 52) does not affect the final output data, so that one clock delay circuit 50 is used for the horizontal synchronization 7a waveform into which the data stored in the frame memory 44 is input as shown in FIG. The clock is delayed to be output through the AND gate AN4 and the OR gate OR2.

Because the first and second control signal terminals D and E, which are outputs of the control logic circuit 43, are ″ high ″, the input terminals of the AND gates AN1 and AN3 become ″ low ″ so that the AND gates AN1 and AN3 This is because there is no output, and only the AND gates AN2 and AN4 can select and pass data.

When performing the zoom function, the vertical addresses of the frame memory 44 shown in FIG. 8A are increased one by one when two horizontal synchronizations are input, based on the center point of the screen to be enlarged. When the data is read at a slower rate, a magnified image can be obtained.

Referring to the circuits of FIG. 4 of the present invention, the circuits (46), 47, 48, and 49 in FIG. 4 are vertical linear interpolation circuits of an enlarged screen, and waveforms of 7k from the control logic circuit 43 are shown. Receive the signal of the first control signal stage (D) as shown in the 7m to obtain the output. Then, the data output from the frame memory 44 is delayed by one horizontal synchronizing period by the 1H delay circuit 46 of one horizontal line, and this is added to the frame memory 44 by the first adder 47 to the output value. Divide by two at the first half-life 48.

Therefore, the average value of the data output through the first half-life 48 and the data read out of the frame memory 44 is obtained through the AND gates AN1 and AN2 and the OR gate OR1, and the average value is obtained from the control logic circuit ( 43 is inserted into the extended vertical line.

The one clock delay circuit 50, the second adder and the half-life 51, 52, the AND gates AN3, AN4, and the OR gate OR2 are horizontal interpolation circuits when they are enlarged and are output to the control logic circuit 43. The second control signal stage E, i.e., the " low " signal of FIG. 7l is input to the AND gates AN3 and AN4 to obtain a final output as shown in FIG. That is, the data passing through the ORA, which is the vertical linear interpolation circuit, is added from the first adder 51 and the same data as the seventh degree obtained through the one clock delay circuit 50 to the second half-life 52 to two. It is divided and averaged, and its output is passed through the AND gate AN3 because the second control signal terminal E of the control logic circuit 43 is ″ low ″, and the final output as shown by (7o) through the oragate OR2. Becomes

In this way, the original screen as shown in FIG. 8A is reconstructed into a screen interpolated horizontally and vertically as shown in FIG. Here, the final data of each line is incorrectly interpolated. Since the data is included in the overlapping part of the actual TV screen configuration, it is invisible to the human eye.

In an embodiment of the present invention, vertical linear interpolation is performed first, and horizontal linear interpolation is performed later. However, those skilled in the art may use horizontal linear interpolation prior to the data read from the frame memory 44 as opposed to the present invention. Note that the same final result can be easily obtained later with vertical linear interpolation.

As described above, when sequential scan type TV which stores and transmits video signals divided into excellent and excellent fields at once and reads them sequentially in frame memory, the video signals are manually and horizontally interpolated horizontally. There is an advantage of preventing roughening.

Claims (1)

In the screen magnification circuit of a progressive scan type television having a frame memory 44 storing odd and excellent field image data, a horizontal synchronous signal and a clock stage input through a horizontal signal input terminal 41 detected from a synchronous detection circuit. A control logic circuit 43 for generating a selection addressing signal of image data according to vertical / horizontal expansion and a data selection control signal according to vertical / horizontal linear interpolation by the basic clock signal inputted to (42); And a frame memory 44 to digitize the image signal and store the enlarged data according to an address signal according to vertical and horizontal enlargement of the control logic circuit 43 and the frame memory 44. A 1H line delay circuit 46 for delaying the output by 1H, a first adder 47 for adding the output of the frame memory 44 and the output of the 1H line delay circuit 46, A first half-life 48 that divides the output of the first adder 47, and an output of the frame memory 44 and an output of the first half-life 48 along the output of the control logic circuit 43. An oragate OR1 to select the AND gates AN1 and AN2 to be selected, the outputs of the AND gates AN1 and AN2, and a one clock delay circuit 50 to delay the output of the oragate OR1 by one clock. A second adder 51 for adding the output of the first clock delay circuit 50 and the output of the vertical linear interpolation, a second half-life 52 for dividing the output of the second adder 51 by two, and And gates AN3 and AN4 for selecting and finally selecting outputs of the first clock delay circuit 50 and the second half-life 52 according to the second control signal of the control logic circuit 43, and the AND gate ( The screen magnification circuit of the progressive scan television system, characterized in that it comprises an OR gate (OR2) sum the outputs of AN3, AN4).

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