KR910020869A - Passage-free 2-metal tape self-adhesive system - Google Patents

Passage-free 2-metal tape self-adhesive system Download PDF

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KR910020869A
KR910020869A KR1019910007471A KR910007471A KR910020869A KR 910020869 A KR910020869 A KR 910020869A KR 1019910007471 A KR1019910007471 A KR 1019910007471A KR 910007471 A KR910007471 A KR 910007471A KR 910020869 A KR910020869 A KR 910020869A
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dielectric layer
providing
lead
signal
dielectric
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KR1019910007471A
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매타 패리드
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원본 미기재
휴렛트 팩카드 캄파니
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음No content

Description

무통로 2-금속 테이프 자동 접착시스템Passage-free 2-metal tape self-adhesive system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제7도는 본 발명의 일 실시 태양에 따른 무통로 2-금속 TAB구조의 부분적인 개략사시도, 제8도는 본 발명의 제1실시 태양에 따른 두 개의 접지면을 포함하는 무통로 3-금속 TAB구조의 부분적인 개략도, 제9a도는 본 발명의 구조를 제조하는데 사용될 수 있는 제조공정중의 하나를 도시한 도면, 제9b도는 두 개의 단일 금속 TAB 프레임구조, 회로 TAB 프레임 및 접지면 TAB 프레임이 함께 아교로 붙여져 무통로 2-금속 TAB 어셈블리가 형성됨을 도시한 도면.7 is a partial schematic perspective view of a pathless 2-metal TAB structure according to an embodiment of the present invention, and FIG. 8 is a pathless 3-metal TAB structure comprising two ground planes according to the first embodiment of the present invention. Partial schematic diagram of FIG. 9A illustrates one of the fabrication processes that can be used to fabricate the structure of the present invention, FIG. 9B depicts two single metal TAB frame structures, a circuit TAB frame and a ground plane TAB frame together. Showing that a painless two-metal TAB assembly is formed.

Claims (11)

근접 이격된 다수의 전도체를 가진 디바이스에 대한 인터페이스를 제공하는 장치(100)로서, 제1면(102a) 및 제2면(102b)을 가지며, 절연물을 제공하는 제1유전체 수단(102)과; 상기 제1유전체 수단(102)의 상기 제2면(102b)에 접속되며 전기적 결합물을 제공하는 제1신호리이드 수단(104)과; 상기 제1유전체 수단(102)의 상기 제1면(102a)에 결합되며 전기적 인터페이스를 감소시키는 제1신호 인터페이스 최소화 수단(105)으로서, 상기 제1유전체 수단(102)을 통과하지 않으며 전기적 결합물을 제공하는 제1신호 인터페이스 최소화 리이드수단(106)을 포함하는 상기 제1신호 인터페이스 최소화 수단(105)을 포함하는 장치(100).An apparatus (100) for providing an interface to a device having a plurality of conductors in close proximity, comprising: first dielectric means (102) having a first side (102a) and a second side (102b) and providing an insulator; First signal lead means (104) connected to said second surface (102b) of said first dielectric means (102) and providing an electrical coupling; A first signal interface minimization means (105) coupled to the first surface (102a) of the first dielectric means (102) and reducing the electrical interface, the electrical combination not passing through the first dielectric means (102). Apparatus (100) comprising said first signal interface minimizing means (105) comprising a first signal interface minimizing lead means (106) for providing. 제1항에 있어서, 상기 제1신호리이드 수단(104)과 상기 제1신호 인터페이스 최소화 리이드수단(106)은 대체로 동편면상에 놓이는 장치(100).The apparatus (100) of claim 1, wherein said first signal lead means (104) and said first signal interface minimizing lead means (106) are generally placed on a coaxial surface. 제1항에 있어서, 상기 제1신호리이드 수단(104)에 부착되며 절연물을 제공하는 제2유전체 수단(107)과; 상기 제2유전체 수단(107)에 결합되며 전기적 인터페이스를 감소시키는 제2신호 인터페이스 최소화 수단(108)으로서, 상기 제2유전체 수단(107)을 통과하지 않으며 전기적 인터페이스를 감소시키는 제2신호 인터페이스 최소화 리이드수단(109)을 포함하는 상기 제2신호 인터페이스 최소화 수단(108)을 더 포함하는 장치(100).A second dielectric means (107) attached to said first signal lead means (104) and providing an insulator; A second signal interface minimization means (108) coupled to the second dielectric means (107) for reducing the electrical interface, the second signal interface minimizing lead for reducing the electrical interface without passing through the second dielectric means (107). The apparatus (100) further comprising said second signal interface minimizing means (108) comprising means (109). 절연물을 제공하는 제1평면형 유전체 수단(112a)과; 상기 제1평면형 유전체 수단(112a)에 접착되며 전기적 결합물을 제공하는 신호 전도체 수단(114)으로서, 전기적 결합물을 제공하며 부분적으로 경사진 신호리이드 수단(115)에 결합된 상기 신호 전도체 수단(114)과; 상기 제1평면형 유전체 수단(112a)에 고착되며 전기적 결합물을 제공하는 접지된 전도체 수단(116)으로서, 접지결합물을 제공하는 접지리이드 수단(117)을 포함하는 상기 접지된 전도체 수단(116)과; 상기 접지된 전도체 수단(116)에 부착되며 절연물을 제공하는 제2평면형 전도체 수단(112b)을 포함하는 인터페이스 장치(100).First planar dielectric means 112a for providing an insulator; A signal conductor means 114 adhered to the first planar dielectric means 112a and providing an electrical coupling, the signal conductor means coupled to a partially inclined signal lead means 115 providing an electrical coupling; 114); Grounded conductor means 116 secured to the first planar dielectric means 112a and comprising ground lead means 117 providing a ground bond, wherein the grounded conductor means 116 comprises a ground lead means 117. and; Interface device (100) comprising a second planar conductor means (112b) attached to said grounded conductor means (116) and providing insulation. 2-금속 무통로 TAB프레임 장치(100)로서, 제1면(102a) 및 제2면(102b)을 가진 제1유전체 층(102)과; 상기 제1유전체 층(102)의 상기 제2면(102b)에 결합된 제1신호리이드(104)와; 상기 제1유전체층(102)의 상기 제1면(102a)에 결합된 제1접지면(105)으로서, 상기 제1유전체층(102)을 통과하지 않는 제1접지리이드(106)를 포함하는 상기 제1접지면(105)을 포함하는 장치(100).2. A two-metal passageless TAB frame apparatus, comprising: a first dielectric layer 102 having a first side 102a and a second side 102b; A first signal lead (104) coupled to the second surface (102b) of the first dielectric layer (102); The first ground plane 105 coupled to the first surface 102a of the first dielectric layer 102, wherein the first ground lead 106 does not pass through the first dielectric layer 102; A device 100 comprising a ground plane 105. 제5항에 있어서, 상기 제1신호리이드(104) 및 상기 제1접지리이드(106)는 대체로 동평면 상에 놓이는 장치(100).6. The apparatus (100) of claim 5, wherein said first signal lead (104) and said first ground lead (106) lie generally coplanar. 제5항에 있어서, 상기 제1신호리이드(104)에 부착된 제2유전체층(107)과; 제2유전체층(107)에 결합된 제2접지면(108)으로서, 상기 제2유전체층(107)을 통과하지 않는 제2접지면리이드(109)를 포함하는 상기 제2접지면(108)을 더 포함하는 장치(100).A second dielectric layer (107) attached to said first signal lead (104); The second ground plane 108 coupled to the second dielectric layer 107, further comprising the second ground plane 108 including a second ground lead 109 that does not pass through the second dielectric layer 107. Including device 100. 이중의 단일-금속 TAB 프레임 장치(110c)로서 제1유전체층(112a)과, 상기 제1유전체층(112a)에 접착된 다수의 전도체 리이드(114)와; 상기 제1유전체층(112a)에 아교접착되며, 접지리이드(117)에 접속된 접지면(116)과; 상기 접지면(116)에 부착된 제2유전체층(112b)을 포함하는 장치(110c).A dual single-metal TAB frame device (110c) comprising: a first dielectric layer (112a) and a plurality of conductor leads (114) bonded to the first dielectric layer (112a); A ground plane 116 glued to the first dielectric layer 112a and connected to a ground lead 117; And a second dielectric layer (112b) attached to the ground plane (116). 다수의 근접 이격된 전도체를 가진 디바이스에 대한 인터페이스를 제공하는 장치로서, 제1면과 제2면을 가진 절연성 캐리어 필름(120)과; 상기 필름(120)의 상기 제1면에 부착된 제1의 다수의 전도성 소자(122)와; 상기 필름(120)의 상기 제2면에 부착된 제2의 다수의 전도성 소자(124)와; 상기 제1 및 제2의 다수의 전도성 소자(122 및 124)의 각각을 종단하는 다수의 내측 및 외측리이드(126 및 128)로서, 상기 제1 및 제2의 다수의 전도성 소자(122 및 124)중의 어느 하나와 대체로 동평면 상에 정렬되는 상기 다수의 내측 및 외측리이드(126 및 128)를 포함하는 장치.An apparatus for providing an interface to a device having a plurality of closely spaced conductors, the apparatus comprising: an insulating carrier film (120) having a first side and a second side; A first plurality of conductive elements (122) attached to the first surface of the film (120); A second plurality of conductive elements (124) attached to the second surface of the film (120); A plurality of inner and outer leads 126 and 128 terminating each of the first and second plurality of conductive elements 122 and 124, the first and second plurality of conductive elements 122 and 124 And said plurality of inner and outer leads (126 and 128) aligned generally coplanar with either one. 다수의 근접 이격된 전도체를 가진 디바이스에 대한 인터페이스를 제공하는 장치로서, 제1면과 제2면을 가진 절연성 캐리어 필름(120)과; 상기 필름(120)의 상기 제1면에 부착된 제1의 다수의 전도성 소자(122)와; 상기 필름(120)의 상기 제2면에 부착된 제2의 다수의 전도성 소자(124)와; 상기 제1 및 제2의 다수의 전도성 소자(122 및 124)의 각각을 종단하는 다수의 내측 및 외측리이드(126 및 128)로서, 상기 다수의 내측리이드(126)는 상기 제1의 전도성 소자(122)와 대체로 동평면 상에 정렬되게 하고 상기 다수의 외측리이드(128)는 상기 제2다수의 전도성 소자(124)와 대체로 동평면 상에 정렬되게 한 상기 다수의 내측 및 외측리이드(126 및 128)를 포함하는 장치.An apparatus for providing an interface to a device having a plurality of closely spaced conductors, the apparatus comprising: an insulating carrier film (120) having a first side and a second side; A first plurality of conductive elements (122) attached to the first surface of the film (120); A second plurality of conductive elements (124) attached to the second surface of the film (120); A plurality of inner and outer leads 126 and 128 terminating each of the first and second plurality of conductive elements 122 and 124, wherein the plurality of inner leads 126 are formed of the first conductive element ( The plurality of inner and outer leads 126 and 128 such that the plurality of outer leads 128 are aligned substantially coplanar with the second plurality of conductive elements 124. Device). 2-금속 무통로 TAB프레임을 제조하는 방법으로서,제1면 및 제2면을 가진 제1유전체 층(102a)을 제공하는 단계와; 상기 제1유전체층(112a)의 상기 제1면에 신호트레이스(114)를 부착하는 단계와; 제1면 및 제2면을 가진 제2유전체층(112b)을 제공하는 단계와; 접지트레이스(117)를 포함하는 접지면(116)을 상기 제2유전체층(112b)의 상기 제1면에 부착하는 단계와; 상기 제1유전체층(112a)을 상기 접지면(116)에 부착하는 단계를 포함하는 방법.A method of making a two-metalless TAB frame, comprising: providing a first dielectric layer (102a) having a first side and a second side; Attaching a signal trace (114) to the first surface of the first dielectric layer (112a); Providing a second dielectric layer (112b) having a first side and a second side; Attaching a ground plane (116) comprising a ground trace (117) to said first surface of said second dielectric layer (112b); Attaching the first dielectric layer (112a) to the ground plane (116). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910007471A 1990-05-10 1991-05-09 Passage-free 2-metal tape self-adhesive system KR910020869A (en)

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US52228990A 1990-05-10 1990-05-10

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DE10142483B4 (en) 2001-08-31 2006-12-14 Infineon Technologies Ag Electronic component with external flat conductors and a method for its production
DE10339762B4 (en) 2003-08-27 2007-08-02 Infineon Technologies Ag Chip stack of semiconductor chips and method of making the same
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US4801999A (en) * 1987-07-15 1989-01-31 Advanced Micro Devices, Inc. Integrated circuit lead frame assembly containing voltage bussing and distribution to an integrated circuit die using tape automated bonding with two metal layers
US5028983A (en) * 1988-10-28 1991-07-02 International Business Machines Corporation Multilevel integrated circuit packaging structures
US4912547A (en) * 1989-01-30 1990-03-27 International Business Machines Corporation Tape bonded semiconductor device

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