KR910017532A - Method for forming epitaxial layer of silicon wafer - Google Patents
Method for forming epitaxial layer of silicon waferInfo
- Publication number
- KR910017532A KR910017532A KR1019900002993A KR900002993A KR910017532A KR 910017532 A KR910017532 A KR 910017532A KR 1019900002993 A KR1019900002993 A KR 1019900002993A KR 900002993 A KR900002993 A KR 900002993A KR 910017532 A KR910017532 A KR 910017532A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon wafer
- epitaxial layer
- forming epitaxial
- forming
- wafer
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
- H01L21/30621—Vapour phase etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900002993A KR0185985B1 (en) | 1990-03-07 | 1990-03-07 | Method for forming epitaxial layer in silicon wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900002993A KR0185985B1 (en) | 1990-03-07 | 1990-03-07 | Method for forming epitaxial layer in silicon wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910017532A true KR910017532A (en) | 1991-11-05 |
KR0185985B1 KR0185985B1 (en) | 1999-04-15 |
Family
ID=19296735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900002993A KR0185985B1 (en) | 1990-03-07 | 1990-03-07 | Method for forming epitaxial layer in silicon wafer |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0185985B1 (en) |
-
1990
- 1990-03-07 KR KR1019900002993A patent/KR0185985B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0185985B1 (en) | 1999-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0464515A3 (en) | Method of manufacturing silicon nitride film | |
DE69431385D1 (en) | Process for the production of silicon semiconductor wafers | |
DE69119367D1 (en) | Fastening method and device for wafers | |
GB2249867B (en) | Method for forming field oxide layer of semiconductor device | |
EP0506416A3 (en) | Manufacturing method of soi substrate having monocrystal silicon layer on insulating film | |
JPS52117060A (en) | Method of cleaning silicon wafers | |
KR900008635A (en) | Anti-fog device for semiconductor wafers | |
KR880700449A (en) | Method for preventing autodoping of epitaxial layer and semiconductor device using same | |
KR880701459A (en) | Planner process for forming bias on silicon wafer | |
KR900700556A (en) | Silicon wafer polishing compound | |
DE69333843D1 (en) | Etching process for silicon substrate | |
KR900008697A (en) | Semiconductor wafer manufacturing method | |
IT1173651B (en) | METHOD FOR GROWING MONOCRYSTALLINE SILICON ON A MASKING LAYER | |
KR890700175A (en) | Manufacturing method of silicon carbide | |
KR910017532A (en) | Method for forming epitaxial layer of silicon wafer | |
KR900013596A (en) | Etching method of compound semiconductor | |
EP0603780A3 (en) | Method of growing compound semiconductor on silicon wafer. | |
EP0370919A3 (en) | Method for evaluation of transition region of silicon epitaxial wafer | |
GB8811445D0 (en) | Method of forming epitaxial layer of silicon | |
IT1177642B (en) | PROCEDURE FOR EPITAXIAL DEPOSITION OF SEMICONDUCTOR LAYERS | |
KR960015716A (en) | Semiconductor epitaxial deposition method | |
AU585646B2 (en) | Method of forming polycrystalline silicon layer on semiconductor wafer | |
JPS5789226A (en) | Method of etching silicon nitride layer | |
DE59204451D1 (en) | Process for the areal connection of silicon semiconductor wafers. | |
KR920005323U (en) | Bolt for forming epitaxial layer of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |