KR910012901A - Optimization of Real-Time 2'S Complement Code Multiplier - Google Patents

Optimization of Real-Time 2'S Complement Code Multiplier Download PDF

Info

Publication number
KR910012901A
KR910012901A KR1019890020078A KR890020078A KR910012901A KR 910012901 A KR910012901 A KR 910012901A KR 1019890020078 A KR1019890020078 A KR 1019890020078A KR 890020078 A KR890020078 A KR 890020078A KR 910012901 A KR910012901 A KR 910012901A
Authority
KR
South Korea
Prior art keywords
subtotal
value
decoding
bits
significant bit
Prior art date
Application number
KR1019890020078A
Other languages
Korean (ko)
Other versions
KR920006324B1 (en
Inventor
심대윤
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890020078A priority Critical patent/KR920006324B1/en
Publication of KR910012901A publication Critical patent/KR910012901A/en
Application granted granted Critical
Publication of KR920006324B1 publication Critical patent/KR920006324B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)

Abstract

내용 없음.No content.

Description

실시간 2′S콤플리멘트 코드 승산기의 최적화방법Optimization of Real-Time 2 ′S Complement Code Multiplier

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도-제5도는 본 발명의 블럭도.3 to 5 are block diagrams of the present invention.

Claims (1)

실시간2의 보수코드 승산기의 최적화 방법에 있어서, n비트(ynyn-1yn-2…y1)피승수의LSB측으로 부터 두번째, 첫번째 비트 및0(y2y1o)를 m비트(XmXm-1…X1)의 승수와 디코딩하는 제1디코딩부, 상기 제1디코딩 값과 n비트 초기값(0)의 최상위 비트를 논리합하여 새로운 최상위 비트를 설정하는 제1논리조합부, 상기 제1디코딩 값과 상기 제1논리값의 각 최상위 비트를 제외한 나머지 비트를 가산하는 제1가산부, 상기 제1논리값과 제1가산값을 래치하여 제1부분합을 산출하는 제1부분합 래치부로 이루어진 제1부분합 산출수단과, 상기 피승수의 LSB측으로 부터 K+1, K+2, K+3번째 비트를 상기 승수와 디코딩하는 제K디코딩부, 상기 제K디코딩값과 소정비트 확장된 상기 K-1부분합의 최상위 비트를 논리합하여 새로운 최상위 비트를 설정하는 제K논리조합부, 사이 제K코딩값과 소정비트 확정된 상기 제K-1부분합의 각 최상위 비트를 제외한 나머지 비트를 가산하는 제K가산부, 상기 제K논리값과 상기 제K가산 값을 래치하여 제K부분합을 산출하는 제K부분합 래치부와 상기 제K-1부분합의 LSB측2비트를 래치하는 제K-1래치부로 이루어진 제K부분합 산출수단이 상기 K가 2부터 n보다 첫번째로 작은 짝수까지 변하도록 구성됨을 특징으로 하는 회로.A method of optimizing a real-time two's complement code multiplier, wherein n bits (y n y n-1 y n-2 ... y 1 ) are the second, first bits, and 0 (y 2 y 1 o) from the LSB side of the multiplicand. A first decoding unit for decoding a multiplier of (X m X m-1 ... X 1 ) and a first logical combination that logically combines the most significant bit of the first decoding value and the n-bit initial value (0) to set a new most significant bit. A first adder which adds the remaining bits except for the most significant bit of the first decoding value and the first logical value, and a first subtractor that latches the first logical value and the first addition value to calculate a first subtotal A first subtotal calculating means comprising a subtotal latch unit, a Kth decoding unit for decoding K + 1, K + 2, and K + 3th bits from the LSB side of the multiplicand with the multiplier, and the Kth decoding value and a predetermined bit extension A K-th logical combining unit for setting a new most significant bit by ORing the most significant bits of the K-1 subtotals; A K-adder for adding a K-coding value and the remaining bits except for the most significant bit of the K-th subtotal of the predetermined bit, and calculating the K-subtotal by latching the K-th logical value and the K-th addition value. The Kth subtotal calculating means comprising the Kth subtotal latch portion and the K-1th latch portion for latching the LSB side 2 bits of the K-1th subtotal is configured such that K varies from 2 to the first smaller than n. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020078A 1989-12-29 1989-12-29 Optimization method of 2's complement code multplier KR920006324B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020078A KR920006324B1 (en) 1989-12-29 1989-12-29 Optimization method of 2's complement code multplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020078A KR920006324B1 (en) 1989-12-29 1989-12-29 Optimization method of 2's complement code multplier

Publications (2)

Publication Number Publication Date
KR910012901A true KR910012901A (en) 1991-08-08
KR920006324B1 KR920006324B1 (en) 1992-08-03

Family

ID=19294116

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020078A KR920006324B1 (en) 1989-12-29 1989-12-29 Optimization method of 2's complement code multplier

Country Status (1)

Country Link
KR (1) KR920006324B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100362186B1 (en) * 1995-12-29 2003-03-28 주식회사 하이닉스반도체 Serial booth multiplier using multiplexer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100362186B1 (en) * 1995-12-29 2003-03-28 주식회사 하이닉스반도체 Serial booth multiplier using multiplexer

Also Published As

Publication number Publication date
KR920006324B1 (en) 1992-08-03

Similar Documents

Publication Publication Date Title
JPS6433673A (en) Execution of viterbi algorithm by parallel computation processing structure
JPS6410356A (en) Signal generator
KR910006838A (en) Digital addition circuit
KR910012901A (en) Optimization of Real-Time 2'S Complement Code Multiplier
KR910001535A (en) Multiplication Method and Circuit of Real-Time 2'S Complement Code Numeric Code in Digital Signal Processing System
KR910014801A (en) High Performance Adder Using Carry Prediction
EP0278529A3 (en) Multiplication circuit capable of operating at a high speed with a small amount of hardware
JPH0157372B2 (en)
SE9203683L (en) Device for converting a binary floating point into a 2 logarithm in binary form or vice versa
KR940015793A (en) Binary multiplication implemented by less modified existing hardware
JP3071607B2 (en) Multiplication circuit
JP3530547B2 (en) Minimum delay leading one detector with resultant bias control
KR910018920A (en) Discrete Cosine Transform Integrated Circuit Using Neural Network
KR840006090A (en) Antacid furnace
SU1203511A1 (en) Pipeline arithmetic unit
SU1141401A1 (en) Device for calculating difference of two numbers
RU2037268C1 (en) Binary-coded-decimal-code-8-4-2-1-to-code-5-4-2-1 converter
RU2010311C1 (en) Device for parallel division of real numbers
SU682907A2 (en) Frequency-pulse multiplying and dividing device
SU401994A1 (en) DEVICE FOR DETERMINATION OF MINORANT BINARY CODES
Bauer et al. A limit cycle suppressing arithmetic format for digital filters
SU1406593A1 (en) Device for determining inverse value of number
SU1401456A1 (en) Digital device for computing the logarithm of a number
SU788107A1 (en) Number adding device
SU1662007A1 (en) Device for code checking

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970829

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee