KR910009847B1 - Image memory - Google Patents

Abstract

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Description

Video memory

1 is a schematic diagram illustrating a first embodiment of the present invention.

2 is a time chart for explaining an operation example of the embodiment of FIG.

3 is a time chart for explaining another example of the operation of the embodiment of FIG.

4 is a circuit diagram specifically showing an R.Req timing generator used in the embodiment of FIG.

5 is a circuit diagram specifically showing a W.Req timing generator used in the embodiment of FIG.

6 is a circuit diagram specifically showing a REF.Req timing generator used in the embodiment of FIG.

FIG. 7 is a time chart for explaining the operation of the circuit shown in FIGS.

FIG. 8 is a circuit diagram specifically showing a cycle generator used in the embodiment of FIG.

9 is a time chart for explaining the operation of the circuit diagram of FIG.

10 is a schematic diagram illustrating a second embodiment of the present invention.

11 is a time chart for explaining an example of the operation of the embodiment of FIG.

12 is a time chart for explaining another example of the operation of the embodiment of FIG.

FIG. 13 is a circuit diagram specifically showing a generator for generating a latch pulse signal to the SEL.R and R registers supplied to the address generator of the embodiment of FIG.

FIG. 14 is a time chart for explaining an operation example of the circuit diagram of FIG.

FIG. 15 is a time chart illustrating the operation of the embodiment of FIG. 10 when W. CLK is controlled by the CGW.

FIG. 16 is a circuit diagram showing a generator for generating a cycle signal to control the address generator used in the second embodiment.

17 is a time chart illustrating the operation of the FIG. 16 circuit.

18 is a schematic diagram illustrating a modification of the second embodiment.

FIG. 19 is a time chart for explaining modification of the embodiment of FIG. 18. FIG.

20 is a schematic diagram illustrating a third embodiment of the present invention.

21 is a time chart for explaining the operation of the embodiment of FIG.

FIG. 22 is a time chart illustrating the operation of the embodiment of FIG. 20 when arbitrarily performing read reset.

FIG. 23 is a time chart illustrating the operation of the embodiment of FIG. 20 when arbitrarily performing read and write reset.

24 is a circuit diagram specifically showing a W counter, a W. Req generator, and a W. load generator used in the embodiment of FIG. 20;

FIG. 25 is a circuit diagram specifically showing an R counter, an R.Req generator and an R. load generator used in the embodiment of FIG. 20. FIG.

26 is a schematic diagram illustrating a modification of the third embodiment.

The present invention relates to an image memory capable of storing and reproducing a video signal, in particular an image memory suitable for digital signal processing by delaying a sampled and quantized video signal by a predetermined time.

Video memory, which delays or memorizes sampled and quantized video signals at predetermined intervals, is used as a basic component of high-definition television systems, multi-function video tape recorders, and digital television systems. It became.

Conventionally, as a video memory of such a system, a general-purpose dynamic RAM (DRAM) having a low price per bit is connected and used in parallel. However, in recent years, the memory capacity per chip has increased to 256K or 1M bits, so that the memory capacity required for video signal processing is realized with one chip, and the conventional method of connecting several memories in parallel deteriorates the utilization efficiency of the memory capacity. There was a problem.

In particular, since the cycle time is delayed in the dynamic memory, high-speed data such as a normal video signal is serially / parallel-converted into N bits (N is an integer) at a time to reduce the speed of the high-speed data, and then write / read the memory. Run For this purpose, a large number of memories are required, and especially when using a large-capacity general-purpose memory having a low cost per bit, there are many unused regions of the memory, thereby degrading the utilization efficiency in the direction of the word.

To overcome this problem, described in “320-degree × 700 columns of screen-only serial input / output dynamic memory for field memory for televisions and VTRs”, Nikkei Electronics, February 11, 1985, p219-239. As described above, a dynamic memory for a high speed serial input / output operation of data corresponding to one horizontal scanning line has been devised recently. However, even in the above memory, in order to improve the resolution, a system in which the sampling frequency is made four times the color carrier frequency (hereinafter referred to as fsc), or by randomly removing the data written from the memory and the read data of the memory, For example, implementing the function of reducing and enlarging the screen becomes very complicated in the sub-circuit configuration, making it difficult to have a general function as video signal processing.

In the prior art, a read clock signal (hereinafter referred to as R. CLK) used for reading data from the image memory and a write clock signal (hereinafter referred to as W.CLK) used to write data from the image memory are referred to. Since the cycle is not set independently, for example, the reduced screen created by increasing the cycle of W.CLK and wiping out the write data (hereinafter referred to as Din) is discarded from memory and the cycle of R.CLK is increased to read data. There is a problem in that the external circuit configuration of the memory becomes complicated when the enlargement function or the like by expanding (hereinafter referred to as Dout) is realized.

In addition, in the above-described conventional example, if the additional function of randomly accessing the memory at the externally designated address is lacking, for example, "picture and picture" for displaying two different images in the same screen. If the screen memory is to realize a function or a function of displaying other information on a part of the screen, there is a problem that the external circuit configuration is significantly complicated.

In addition, in the conventional memory, simultaneous write / read of high-speed serial data is not executed, and digital processing of continuous video signals in real time is inconvenient. That is, in the conventional configuration, a single data register corresponding to one line is provided at the input / output terminal of the memory cell array, and the write and read operations are shared, and between the memory cell array and the data register in units of data corresponding to one line. Enable data transfer. Thus, for example, when a continuous video signal is input, the memory is always in the write mode so that data of the preceding field is not read from the memory at the same time. Therefore, it is necessary to provide separate video memories for read / write which simultaneously perform write and read operations.

Moreover, in order for the memory cell array to perform transfer in units of data corresponding to one line, the delay time should be set only in units of data corresponding to one line, and it becomes difficult to set it to an arbitrary value.

The object of the present invention is to eliminate the above-mentioned problems of the prior art, and to enable the cycles of W.CLK and R.CLK to be set independently so that the above functions are easily realized, for example, data writing in the blanking period of a video signal. By stopping the operation, the utilization efficiency of the memory capacity is increased.

Another object of the present invention is to provide a video memory that is capable of high-speed input / output, for example, multi-function processing such as displaying two different pictures in multiple portions of a screen, or normal video signal processing.

It is still another object of the present invention to provide an image memory capable of simultaneous writing / reading of high speed serial data and setting the delay time to an arbitrary value without being fixed in data units corresponding to one line.

According to an embodiment of the present invention, a gate circuit capable of arbitrarily removing a master clock signal (hereinafter referred to as CL) for controlling the image memory is provided separately for the write and the read, and is controlled by another control signal in the gate circuit. The clock signal is provided with a W.CLK that closes the data signal Din and an R.CLK that outputs the data signal Dout, and a counter that counts W.CLK (hereinafter referred to as W counter) and a counter that counts R.CLK (hereinafter referred to as "W.CLK"). A signal (hereinafter referred to as W. Req) and a Dout requesting the start of operation to receive the count decoded values of the W and R counters and write the data, which is abolished as Din, to the memory cell array. Each of the request generators for generating a signal (hereinafter referred to as R.Req) for requesting the start of operation to read data for the data from the memory cell array is provided. Is achieved.

According to another embodiment of the present invention, a counter for counting CLK and stopping the count operation when the count value is initially set by a reset signal (hereinafter referred to as RES) and the count value reaches a predetermined value (hereinafter referred to as CLK counter). Stops the count of the R counter during the count operation of the CLK counter, receives the count decoded value from the CLK counter and the count decoded value from the R counter, outputs the R.Req from the R.Req generator, and When the operation for reading data in the array is started, a more suitable video memory can be obtained.

According to another embodiment of the present invention, an image memory includes a memory cell array, a serial / parallel converter for inputting serial data and outputting m-bit parallel data, and a parallel input for converting m-bit parallel data and outputting the serial data. Address controller, time-controlled control signal for writing parallel / serial-converted parallel data to memory cell array and control signal for reading parallel data from memory cell array It consists of an address generator that outputs a write address (exactly, write address data) and a read address (exactly, read address data) to the cell array, wherein the address generator is at least write and read registers, externally arbitrary address data or incremented addresses. Select any of the values An input selector that closes the write and read registers, an output register that selects and outputs any stored values of the write and read registers, and outputs them to the memory register, and simultaneously outputs the values of the memory registers to the memory cell array. And configured to generate an increased or decreased address value guided by the increasing and decreasing means. In this embodiment, one cycle of the address generator is selected until one of the write and read registers is selected and occupied in the memory register and passed through the address increasing / decreasing means is again occupied in the write or read register selected by the input selector. At the same time, during this one cycle another register output is forbidden to be selected and closed in the memory register.

According to still another embodiment of the present invention, the image memory includes serial / parallel conversion means (SP conversion means) for sequentially converting the closed input data into parallel data in units of 2 ⁿ bits (n is a natural number), in units of 2 ⁿ bits. a parallel / serial converting means (PS conversion means) for sequentially converting and outputting the serial data to parallel data to serial data, (K × 2 ⁿ⁾ columns × m lines (where K, m is a natural number) of the memory cell array, SP SP converter converts the input data in the conversion means to count the pulse of the write clock used and outputs a predetermined signal at the time of (L × 2 ⁿ ) count (L is a natural number). The first holding means for holding the converted data at < RTI ID ^{= 0.0} > &^lt; / RTI &^gt; and outputting the output data from the PS converting means to count the pulses of the read clock used and to generate a predetermined signal at the time (J x 2 ⁿ ) Lead count output Second storage means for temporarily holding parallel data input in units of 2 ⁿ bits and inducing parallel data to the PS conversion means in response to the output signal from the read counter, and receiving the output signal of the write and read counter. Cycle generating means for generating write cycles and read cycles for the cell array, address generating means for generating write and read addresses for the memory cell array, reset means for independently resetting the write counter and read counter from each other; 2, which is configured by initial setting means for initially setting the address value of the write address or read address generated by the address generator in synchronization with the reset of the write counter or read counter, and held by the first holding means during the write cycle. ⁿ bits of parallel data are addressed The data is written to the memory cell array in accordance with the write address in the generating means, and parallel data in units of 2 ⁿ bits are read from the memory cell array in accordance with the read address in the address generating means and input to the second holding means during the read cycle.

Hereinafter, as an embodiment of the present invention, an example of the circuit operation will be described using the first and second drawings.

In FIG. 1, the SP converter 3 for serial / parallel conversion is connected to an input terminal 1 for receiving a high speed serial data Din, and is closed at a predetermined clock signal to convert serial data into parallel data and output the same. . The first holding means (hereinafter referred to as an input register) 4 is coupled to the output side of the SP converter 3, and is connected to an external command signal which describes a group of converted m-bit parallel data sent from the SP converter 3 described later. Close it and output it.

The output signal of the input register 4 is introduced into the data storage means (hereinafter referred to as a memory cell array) 5 so that each of the m bits of parallel data is sequentially input to the memory cell array 5. The second holding means (hereinafter referred to as an output register) 6 coupled to the output of the memory cell array 5 stores m-bit parallel data which is the output of the memory cell array 5. The PS converter 7 coupled to the output of the output register 6 converts the input parallel data into serial data and outputs it. The PS converter 7 closes m-bit parallel data in the output register 6 by an external command signal, which will be described later, converts the parallel data that is closed in accordance with an external clock signal into serial data, and outputs the high-speed serial signal at the output terminal 2. Output as data Dout.

In addition, the memory cell array 5 has a write address data signal (hereinafter referred to as a W address signal) for designating an address in the write memory for m-bit parallel data sent from the input register 4, and reading from the output register 6. A bit address data signal specifying an address (hereinafter referred to as an R address signal) and a refresh data signal specifying an address to refresh in the memory (hereinafter referred to as a REF address signal) are input to the memory cell array 5 in time division. An address decoder 8 is provided. The address decoder 8 receives a time division address applied from an address generator 9 operating in accordance with an output signal from the address controller 26.

Here, the configuration of the address controller 26 will be described in detail. The address controller 26 includes a read gate circuit (hereinafter referred to as R gate circuit) 15 corresponding to the read gate signal CGR at the terminal 12 and the system clock signal CLK at the terminal 14, and the write gate signal CGW. And a write gate circuit (hereinafter referred to as a W gate circuit) 16 responsive to CLK. The read clock signal R.CLK that is the output of the R gate circuit 15 and the write clock signal W.CLK that is the output of the W gate circuit 16 are the read counter (hereinafter referred to as R counter) 17 and the write counter (hereinafter W). Respectively).

In addition, a system clock counter (hereinafter referred to as CLK counter) 18 and a refresh counter (hereinafter referred to as REF counter) 20 for counting the non-gateed system clock are provided, and the reset signal RES is provided at the terminal 11. Is entered.

The reset signal and the output signals from the R counter 17 and the CLK counter 18 are ORed in the OR circuit and supplied to the read request (R.Req) generator 23. Similarly, the count values of the W counter 19 and the REF counter 20 are supplied to the write request (W.Req) generator 24 and the refresh request (REF.Req) generator 25. These R.Req, W.Req and REF.Req generators 23, 24 and 25 can receive the output signals from the OR circuit 22, W counter 19 and REF counter 20, respectively. At this time, they generate R.Req, W.Req and REF.Req signals and output them to the cycle generator 10. The cycle generator 10 receives the input R.Req, W.Req, and REF.Req signals, and determines the priority in order of read, write, and refresh, for example, a read cycle (R cycle) signal and a write cycle. (W cycle) and refresh cycle (REF cycle) are supplied to the address generator 9 so that they do not overlap each other. The address generator 9 generates each address signal in time division corresponding to this cycle, and supplies it to the address decoder 8.

The address controller 26 also includes a timing generator 21 for outputting signals of ψ ₀ to ψ _{n obtained} by frequency division of the CLK.

The timing generator 21 is a generator of a signal that determines the timing of generation of a control signal that determines an operation cycle of the address generator 9, for example, frequency division of CLK into 1 / K and frequency division of 1 / K. A signal obtained by phase shifting the signal for each CLK is used as a timing signal.

The reset signal RES at the terminal 11 described above is input to the OR circuit 22, the R counter 17, the CLK counter 18, and the W counter 19, and each counter is reset by the reset signal RES. It becomes setable.

The output signals R.CLK and W.CLK of the R gate circuit 15 and the W gate circuit 16 are also supplied to the PS converter 7 and the SP converter 3, respectively, and are synchronized with the clock signal to output the serial data. Run the output and the input respectively.

In addition, the R.Req generator 23 and the W.Req generator 24 input the R. load signal and the W. load signal to the PS converter 7 simultaneously with the output of the R.Req signal and the W.Req signal, respectively. Output to register (4). Thus, upon receiving the R. load signal, the PS converter 7 closes the m bit parallel data in the output register 6. Similarly, upon receiving the W. load signal, the input register 4 closes m bits in the SP converter 3, and the output m bits of parallel data are stored in the memory cell array 5.

When the input signals at the input terminals 11 to 14 are represented by (2b), (2c), (2e) and (2a), respectively, the outputs of the R. gate circuit 15 and the W. gate circuit 16 are shown. In this case, R. CLK (2d) and W. CLK (2f) are obtained in which CLK 2a is gated separately at CGR and CGW, respectively. These R. CLK 2d and W. CLK 2f are used as clock signals for shifting the PS converter 7 and the SP converter 3 respectively, and are also guided to the R counter 17 and the W counter 19. . Thus, for example, when one bit of Din is closed by the W.CLK 2f in the SP converter 3 and data is shifted, the count value of the W. counter 19 is also increased by one. Similarly, when one bit of parallel data occupied in the PS converter 7 is shifted in series by the R. CLK 2d toward the output terminal 2, the count value of the R. counter 17 is also increased by one. . Here, the respective gate circuits 15 are selected by selecting the count values of the R counter 17 and the W counter 19 to be the same as the values of the bit conversions in the PS converter 7 and the SP converter 3, respectively. Even with R.CLK and W.CLK arbitrarily gated in and (16), all data read in parallel in each PS converter 7 are serially converted and serialized to the closed timing and SP converter 3. The timing at which the SP converter becomes full can be detected as a count value in the data occupied by. In the example of FIG. 2, the bit conversion amounts of the PS converter 7 and the SP converter 3 are 12 bits, and the count values of the R counter 17 and the W counter 19 are selected to 12. In this case, for example, it occurs in a cycle of 12 cycles of R. CLK like the count output signal 2h of the R counter 17.

Although not shown in FIG. 2, the count output signal of the W. counter 19 also occurs in the 12 cycle period of W. CLK. The count value of the REF counter 20 and the count value of the R counter 17 and the W counter 19 are different, and the count value is selected so that the refresh cycle is optimized in the memory cell array 5 and 15 in the example of FIG. Is selected.

Receiving the output signals of the respective counters 17, 19, and 20, R.Req (2i), W.Req (2j) and REF.Req from the respective Req generators 23-25. (2k) is generated, and each cycle is designated as (2 ₀ ) in synchronism with Ø ₀ (2 L) by the cycle generator 10 described in FIGS. 8 and 9. Subjected to a cycle _(20), each address in a time as indicated by the in-address generator (9) (2p) is output. In this method, for example, after serially converting all the parallel data coming into the PS converter 7 from the output buffer register 6 by the R. load 2q, and then again by the R. load 2q. Since R.Req occurs during one cycle (12 bits of R.CLK is one cycle in the example of FIG. 2), R.Req is generated, and R cycles are allocated and read from the memory cell array 5 according to the R address. The data is transferred to the output buffer register, and preparation for transferring new data to the PS converter 7 is executed again. This enables continuous read of the output signal Dout of high speed serial data as shown in (2s). After the serial Din is closed by the conversion bits for the SP converter 3, the data is transferred in parallel to the input buffer register 4 according to the W. load 2r, and the new serial Din is again closed by the conversion bits. Therefore, W.Req occurs during one cycle (12 bits of W.CLK is one cycle in the example of FIG. 2), W cycles are allocated, and the memory cell array (in the input buffer register 4) The data write to 5) is executed, and again preparation for transferring parallel data from the SP converter 3 to the input buffer 4 is executed. This enables continuous writing of high speed serial data Din as shown in (2t).

In addition, the CLK counter 18 and the OR circuit 22 are provided to detect the count value of the counter 18 that counts the CLK even during the period in which the R. CLK 2d is stopped, and the R.Req generator 23 is detected. Output to generate R.Req.

In addition, RES (2b) is detected and guided to R.Req generator 23 via an OR circuit to generate R.Req. In this case, the CLK counter 18 resets to RES 2b and outputs the set count value 2g, and then stops counting. During the period in which the CLK counter 18 counts, the count of the R. counter 17 stops, and the R counter output signal becomes (2h).

The CLK counter output signal 2g, the R counter output signal 2h, and the RES (2b) are input to the R.Req generator 23, and immediately after the RES (2b) as indicated by (2i). Req is generated, and then R.Req is generated by the counter output signal 2g at the CLK counter 18, and then R.Req is generated by the cycle output signal 2h at the R counter 17. Occurs. After this, as shown by (2o), an R cycle is immediately assigned after RES (2b), and in this R cycle, for example, data of an address value of (O) R is transferred from the memory cell array 5. Is read into the output buffer register 6, is transferred to the PS converter 7 by R. load 2q, and the data in the address order of (O) R, as indicated by (2s), is stored in the CLK counter 18. You can output near the counter value (2g). As a result, data of the initial set address value can be taken more quickly, resulting in a more convenient memory.

3 is a timing chart showing another example of operation of the video memory of FIG. In FIG. 3, each signal of (3a) to (3t) is the same signal as (2a) to (2t) of FIG.

The operation example of FIG. 3 differs from the operation example of FIG. 2 in that the stop periods of the clocks by the CGR 3c and CGW 3e are longer than the CGR 2c and CGW 2e, and are the same. As shown in FIG. 3, R. CLK 3d and W. CLK 3f are generated simultaneously after the CLK counter output signal 3g is generated.

By selecting the CGR 3c and the CGW 3e in this manner, the address timings of the Dout 3s and the Din 3t are as shown, for example, the data of the address 1R is output as Dout. Data input to Din in the period specified is written to address (1) W. Therefore, for example, by using the memory output of this embodiment as the next memory input, data of twice the delay amount can be easily obtained. As shown by (3s), R. CLK (3d) is generated and can be output sequentially from the data of the initial address (O) R. This is efficient in order to prevent data from other addresses from being output when stopping the writing and reading of the blanking period of the video signal and increasing the use efficiency of the memory capacity.

When the CLK 3a is removed by using the CGR (2c) or the CGW (2e), the generation cycle of R.Req (3i) or W.Req (3j) is increased and assigned to each cycle signal 3c. Since the allocation cycle of the R cycle or the W cycle is large, the data of each of Dout (3s) can be extended or the data of Din (3t) can be easily inferred. It will be clear that the reading in the memory of the enlarged screen and the writing in the memory of the reduced screen according to the technique of the present invention can be easily performed.

The R.Req timing generator shown by a dotted line block in FIG. 1 is composed of an R gate circuit 15, an R counter 17, a CLK counter 18, an OR circuit 22, and an R.Req generator 23, The W.Req timing generator consists of a W gate circuit 16, a W counter 19 and a W.Req generator 24, and the REF.Req timing generator consists of a REF counter 20 and a REF.Req generator 25. It is. Next, an example of the hardware configuration of the Req timing generator is described.

4 to 6 are specific examples of the Req timing generator, respectively, and are timing charts showing the seventh operation or the like.

를 NAND하는 것에 의해 NAND 회로(112)의 출력에서 얻어지는 디코드 펄스는 (7e)로 나타낸다. 디코드 펄스(7e)가 “하이”로 되는 동안만, CLK 카운터(17)은 카운터 동작의 실행이 된다. 역으로, NAND 회로(112)의 출력신호(7e)와 RES(7b)의 양쪽이 “하이”인 동안은, R 카운터(18)의 카운트 동작이 정지된다. (7f)는 카운터(63)에서의 캐리어 출력 신호(Co), (7g)는 RES(7b)와 CLK 카운터(17)의 캐리어 출력 신호(7f)의 논리합을 D형 플립플롭(80)에서 래치하여 얻는 출력 신호 Q₁, (7h)는 예를들면 Q₁출력 신호(7g)와 CLK(7a)를 NAND하는 NAND 회로(111)의 출력 신호, (7i)는 R 카운터(18)의 캐리어 출력 신호, (7j)와 (7k)는 Q₂출력과 NAND 회로(114)에서 얻어지는 비슷한 출력 신호, (7l)은 (7h)와 (7k)를 AND한 결과인 R.Req를 나타낸다.4 to 6, (50) to (53) are input terminals of CLK, CGR, RES and CGW, and (54) to (56) are output terminals of R.Req, W.Req and REF.Req. (60) to (75) are counters, (80) to (83) are D flip flops, (90) to (100) are inverters, (110) to (118) are NAND circuits, and (120) to ( 124 is an AND circuit. The R counter 17 and the CLK counter 18 are described as dotted blocks in FIG. 4, the W counter 19 is broken line dotted in FIG. 5, and the REF counter 20 is dotted lines in FIG. As shown. In the timing chart of FIG. 7, (7a) to (7v) show waveforms in the main parts of FIGS. 4, the operation of the circuit will be described first. In FIG. 4, CLK at terminal 50 is represented by (7a), RES at terminal 52 is represented by (7b), CGR at terminal 51 is represented by (7c), and AND circuit 12o. R. CLK of the result of the gate of CLK 7a and CGR 7c is represented by (7d), and the output signals of the counters 60 to 63 are

The decode pulse obtained at the output of the NAND circuit 112 by NAND is denoted by (7e). Only while the decode pulse 7e becomes " high ", the CLK counter 17 becomes the execution of the counter operation. Conversely, while both the output signal 7e of the NAND circuit 112 and the RES 7b are "high", the counting operation of the R counter 18 is stopped. (7f) is a carrier output signal (Co) at the counter 63, (7g) is a logical sum of the carrier output signal (7f) of the RES (7b) and CLK counter 17 in the D-type flip-flop (80) The output signals Q ₁ and 7h obtained by, for example, are the output signals of the NAND circuit 111 for NANDing the Q ₁ output signal 7g and the CLK 7a, and 7i is the carrier output of the R counter 18. Signals 7j and 7k represent similar output signals obtained from the Q ₂ output and NAND circuit 114, and 7l represent R.Req, which is the result of ANDing the 7h and 7k.

Next, the operation of generating W.Req will be described. In FIG. 5, CLK 7a and RES 7b are the same as in FIG. 4, where 7o is CGW at terminal 53, and 7p is CLK 7a at AND circuit 122. In FIG. The result of the gate of the CGW 7o, W. CLK, (7q) is the carrier output signal of the W counter 19, (7r) is a Q obtained by latching the carrier output signal (7q) in the D-type flip-flop 82 _{The 3} output signal (7s) is, for example, W.Req obtained by performing a logical multiplication of the Q ₃ output signal with the inverted signal of CLK 7a.

Next, the operation of generating REF.Req will be described. In FIG. 6, CLK 7a and RES 7b are the same as in FIG. 4, where 7t is the carrier output signal of counter 75, 7u is the carrier output signal at REF counter 20 Q ₄ and the output signal obtained by latching the 7t), (7v) is REF.Req carrier obtained by the method of the same.

Next, a hardware configuration example of the cycle generator 10 constituting the address generator 26 will be described with reference to the drawings. As shown in FIG. 8, in the first embodiment of the cycle generator 10, the input terminal 150 for inputting the Ø ₀ phase signal obtained by frequency division of the CLK in the timing generator 21, R.Req. Input terminals 151, W.Req input terminals 152, REF.Req input terminals 153, and output terminals 154 to 156 for outputting R cycle signals, W cycle signals, and REF cycle signals, respectively. ), (157) to (159) are SR flip flops, (160) and (161) are inverters, (162) and (163) are AND circuits, and (164) to (166) are D flip flops ( 167 to 169 are configured as edge detectors. FIG. 9 is a time chart showing the operation of the embodiment of FIG. 8, and the main part of FIG. 8 operates in accordance with the waveform shown in FIG. For example, when R.Req 9a is input to SR flip-flop 157, Q ₁ output signal 9e becomes " high " and Q ₂ and Q of other flip-flops 158, 159. _{The three} output signals 9f and 9g are gated, and only the Q ₁ output signal 9e is guided to the D-type flip-flops 164 to 166, latched at Ø ₀ (9d), and the R cycle signal ( 9h). The edge detector 169 detects the entire edge 9o of this R cycle signal 9h and is led to the R input of the SR flip-flop so that the Q ₁ output signal 9e is reset to "low". Other cycle preferences operate likewise and as shown in Fig. 9, each cycle signal 9h to 9j does not overlap each other. In this case, the duration of each cycle is set by Ø ₀ .

In this way, R.Req feeds the cycle by the PS converter 7 connected to the output terminal 2 closed by serial data by R.CLK and W.Req is connected to the input terminal 1. The SP converter 3 closes the data serially by W.CLK to supply cycles, and the memory cell array 5 supplies REF.Req in accordance with the refresh cycle so that high-speed serial data is simultaneously stored in the memory. It can be input and output continuously.

As described above, for example, by using each of the Req timing generators in Figs. 4 to 6 and the address generator in Fig. 8, the operation described in the first embodiment of Fig. 1 can be realized without difficulty.

10 illustrates a second embodiment of the present invention.

Compared with the first embodiment of FIG. 1, in the second embodiment, an address arbitrarily designated externally is closed to the address generator 9 as address data SAD continuous in series, for example, serial data Din is stored. When converting into m-bit parallel data, the random access function in units of blocks with m bits as one block is enabled. For this purpose, only the configurations of the address generator 9 and the address controller 26 are different, and the other block configurations are the same as those in the first embodiment of FIG. 1, and the parts of the address generator 9 and the address controller 26 are different. Only the description is omitted.

In the second embodiment, the address controller 26 includes an R gate circuit 15 for gates CGR and CLK, an R counter 17 for counting output signals of the R gate circuit, and a count value of the R counter 17. And an R.Req generator 23 for receiving and operating to output a read request (R.Req) signal. Similarly, the W gate circuit 16 that gates the system clocks CLK and CGW, the W counter 19 that counts the output signal of the W gate circuit, and the count value of the W counter 19 operate to receive the write request (W.Req). A W.Req generator 24 for outputting a signal is included, and a REF counter 20 for counting a system clock CLK that does not gate and a count value of a REF counter are operated to generate a refresh request (REF.Req) signal. An output R. Req generator 25 is provided in the address controller 26. The address controller 26 also inputs the R.Req, W.Req and REF.Req signals to generate a cycle generator 10 and a system CLK that generate control signals for R. cycles, W. cycles and REF cycles. _And a timing generator 21 for frequency division from ₀ to Ø _n . At the time of the R cycle, the cycle generator 10 addresses the read address selection (hereinafter referred to as SEL.R) signal, the read latch (hereinafter referred to as RL) signal and the read register selection (hereinafter referred to as R.SEL) signal. Output to the generator 9. Similarly, at the time of the write cycle, the cycle generator 10 outputs a write address selection (hereinafter referred to as SEL.W) signal, a write latch (hereinafter referred to as WL) and a write register selection (hereinafter referred to as W.SEL) signal, and the REF cycle. At the point of time, the refresh latch (REF.L) signal and the refresh register selection (REF.SEL) signal are output.

In addition, the R.CLK and W.CLK signals are input to the PS converter 7 and the SP converter 3, respectively, as in the embodiment of FIG. 1, and the R. load signal and the W. The W. load signal from the Req generator 24 is input to the PS converter 7 and the input register 4, respectively.

The address generator 9 will be described. The address generator 9 converts the input terminal 27 of the SAD, the input terminal 28 of the SAD strobe (hereinafter referred to as SAS) signal used to fetch the SAD, and externally converts SAD and SAS into a parallel address, which will be described later. A parallel address data register (hereinafter referred to as a TAS) input terminal 29 for a transistor / address strobe (hereinafter referred to as TAS) signal that determines the timing to be transferred to the R register 34 or the W register 35. SAD, SAS and TAS are recorded in SAD Reg (30).

A read address register (R register) 34, a write address register (W register) 35, and a refresh address register (REF register) 36 are provided. The outputs of the registers 34, 35, and 36 are connected to the output selector 37, and any of the R.SEL, W.SEL, and REF.SEL output from the address control circuit 26 described above is output. According to the signal of the arbitrary register of the three registers 34, 35, 36 selects and outputs. A memory address register 38 is connected to the next stage of the output selector 37, and stores the address output by the selection and is output in accordance with the timing signal Ø _m of the timing generator 21.

The output signal of the memory address register 38 is supplied in parallel to the address decoder 8 and the increment register 33. The address value input to the increment register 33 is incremented and supplied to the first and second selectors 31 and 32. In addition, a read address R.Addr and a write address W.Addr in the SAD register are respectively input to the first and second input selectors. When the SEL.R or SEL.W input from the address controller 26 is "high", the data of the SAD Reg 30 is selected, and when the signal is "low", the output value of the increment register 33 is selected. Input to each R register 34 or W register 35. The output value from the increment register 33 is always input to the REF register 36. In addition, the addresses selected by the first and second input selectors 31 and 32 are fetched to the R register 34 or the W register 35 by the latch signals R.L and W.L, respectively.

The operation of the embodiment of FIG. 10 will be described according to the time chart of FIG.

In FIG. 11, 11a is a CLK applied to the terminal 14, and 11b is a set signal SET induced in accordance with SAD, SAS and TAS applied to the terminals 27-29. By the set 116, the R.Reg generator 23 is forcibly generated in synchronization with the CLK 11a.

The R counter 17 and the W counter 19 are forcibly set by the SET 11b to initial values. In the example of FIG. 11, the two counters 17 and 19 and the REF counter 20 operate at the rate of count pulses of 18 clock pulses, and the number of bits of each of the SP converter and PS converter is also selected to 18. do.

In synchronization with the count cycles of the counters 17 and 19, the Req generators 23 to 25 generate Req signals 11c to 11e. 11f is one of signals obtained by dividing CLK by 1 / K frequency in the timing generator 21. When K = 6, basically six signals with different phases Ø ₀ to Ø _S are generated and (11f) is one of the signals Ø ₀ . 11g is a cycle signal, for example, each of Req signals 11c to 11e is generated and assigned to each of the other cycles as the first generation of one cycle of Ø ₀ (11f). However, for example, when R cycles and W cycles occur at the same time, the R cycles are given priority, the priority is given to the W cycles after the R cycles, and each cycle is assigned a time division so that the cycles do not occur at the same time. Adjusted in cycle generator 10. 11h is the R.SEL signal derived from input selector 37 and is generated at the timing of the Ø ₁ phase of the R cycle. When R. SEL 11h enters, the input selector 37 selects the output signal of the R register 34 from the registers 34 to 36 and supplies the selected signal to the memory address register 38. Although not shown, the W.SEL signal is generated in the W cycle, the REF.SEL signal is generated in the REF cycle, and the output signal of one of the registers 34 to 36 is selected according to one of the SEL signals, It is directed to the register 38.

The latch pulse signal for closing the respective output data of the registers 34 to 36 in the memory address register 38 is represented by 11i and fetched in the memory address register 38 by the latch pulse signal 11i. The memory address data is indicated by (11j). The memory address data signal 11j is input to the address decoder 8 and the increment circuit 33. In the memory address data 11j, (K) R denotes an R address of the address value K (exactly, R address data), and (K) W denotes a W address of the address value K (exactly, W address data), (K). REF indicates the REF address (exactly, REF address data) of the address value K. 11k and 11l are SEL.R signals and SEL.W signals input to the first and second selectors 31 and 32, respectively. For example, an SEL.R "high" period is a randomly selected address selected from the SAD register 30 and input to the R register 34, and a SEL.R "low" period is increased in the increasing circuit 33. The address value is selected and input to the R register 34. Similarly, the period in which the SEL.W is "high" is input to the W register 35 by selecting an arbitrarily designated address from the SAD register 30, and the period in which the SEL.W is "low" is increased in the increasing circuit 33. The address value is selected and input to the W register 35. (11o), (11p) and (11q) are the latch pulse signals of the registers 34 to 36, respectively, for example, occurring in the Ø ₄ phase of each cycle, and each of the registers 34 to 36. Fetches an address incremented by the increment circuit 33 or an arbitrarily designated address. 11r, 11s, and 11t are address data signals induced to the R register 34, the W register 35, and the REF register 36. For example, in signal 11r, (N) R is an arbitrarily specified R address derived from SAD register 30 to R register 34 and (N + 1) R is an arbitrarily specified R address value. R address is increased by 1 in 33).

By the operation of the above-described address generator 9, for example, when the number m of parallel bits of the SP conversion is 18, the count value of the R counter 17 is also 18, and the serial inputted after the SET 11b is performed. The data Din 11u is a sequence of (N + 1) W and (N + 2), with 18 bits being one block unit and the write address (N) W arbitrarily designated in the W address period of the memory address signal 11j as an initial address. ) W,… The memory cell array 5 is written to the memory cell array 5. Further, when 18 is selected as the count cycle of the W counter 19, data is read by the output buffer register 6 in the memory cell array 15 in units of 18 bits during the R address period of the memory address signal 11j. do. To this end, the bits of the serial data Dout 11v according to the SET 11b are sequentially assigned to the (N + 1) R, (N + 2) R < / RTI > Is output.

In this case, since there are two blocks of time difference between the serial data Din designated by (N) W and (N) R between the designated serial data Dout, for example, two blocks are divided between (N) W and (N) R. By providing an offset of the address value, the delay amount of Dout is set by the RES signal, so that the delay amount can be easily set in exactly one field or one frame.

As described above, in the embodiment of the present invention, the sum of the clock pulses of the R cycle, the W cycle, and the REF cycle in the address generator 9 is equal to or less than the number of bits m of the SP conversion, for example, as shown in FIG. 6 cycles of clock pulses can be selected to write the high-speed serial data Din and the high-speed serial data Dout at the same time in the video memory, and block-by-block random access can be performed by specifying the SAD. Conforms.

Another operation example of the embodiment of FIG. 10 is shown in FIG. In the example of FIG. 12, the phase of the latch pulse signal latching the selectors 31, 32 and 37 and the registers 34 to 36 and 38 for each cycle in the cycle signal 12g. Is different from the latch pulse signal in the example of FIG. Therefore, in the example of FIG. 11, the serial data Dout 11v outputs data of the arbitrarily designated read address N after two blocks of the SET 11b, whereas in the example of FIG. After one block of the SET 12b, it is possible to output the data of the arbitrarily designated read address N. Next, this will be described in detail.

In Fig. 12, the signals 12a through 12v are the same as the signals 11a through 11v in Fig. 11, but the signals 12h through 12v are slightly different in timing from the signals 11h through 11v. .

In particular, since the R register 34 and the W register 35 operate at the signals 12k to 12t at different timings from the signals 11k to 11t, this portion will be described first. FIG. 13 shows a part of the cycle generator 10 which is a specific generation circuit of the latch pulse signal RL 12o of the SEL.R 12k and the R register 34. As shown in FIG. The operation timing chart of FIG. 13 is shown in FIG. In FIG. 13, reference numerals 170, 171, and 175 denote input terminals that are clock signals of different phases Ø ₅ , Ø ₂ , and Ø ₁ , 172 denotes input terminals of R.Req 14b, and 173. Is the input terminal of the SET 14a, 174 is the input terminal of the R cycle signal 14e, and 176 and 177 are the latch pulse signals 14o of the R register 34 and SEL.R (14h). The output terminals of (), (178) and (179) are flip-flops, (180) to (183) are AND circuits, and (184) are OR circuits.

In FIG. 14, when the SET 14a is input, the Q ₁ output signal 14c of the flip-flop 178 is set to "high", and then "low" by the input R.Req 14b, Q ₂ is as shown in the output signal (14d) of the flip-flop 179 at the next stage. The Q ₂ output signal 14d and the cycle R signal 14e are ANDed together to provide a signal N ₁ (R) 14f, and the N ₁ (R) 14f and the Ø ₁ signal 14g are ANDed together. The signal SEL.R 12h is provided to be used to select an arbitrarily designated R address after SET. R. Req 14b and Ø ₅ signal 14k are logically multiplied so that signal N ₃ (R) 14l is generally used as a latch pulse signal to fetch data from R increment circuit 33 to R register 34. To prepare. Latch pulse signal N ₁ (R) (14f) and Ø ₂ signal (14i), the signal N ₂ (R) is used as a latch pulse signal for fetching the R address data designated arbitrarily within the multiplication logic R register 34 ( 14j). Two signals N ₂ (R) 14j and N ₃ (R) 14l are ORed together and supplied to the R register 34 as a latch pulse signal. On the other hand, the latch pulse signal 12p of the SEL.W 12l and the W register 35 in FIG. 12 is generated by a generator similar to the circuit in FIG. However, in order to generate the SEL.W 12l and the latch pulse signal 12p, instead of the R.Req 14b and the R cycle signal 14e, W.Req 14p and W cycle 14s are used. The two flip-flops 178 and 179 output the Q ₁ (W) signal 14q and the Q ₂ (W) signal 14r, respectively. The Q ₂ (W) signal 14r and the W cycle signal 14s are logically multiplied to provide a signal N ₁ (W) 14t. The signal N ₁ (W) 14t and the signal Ø ₁ (14g) are ANDed together to provide a signal SEL.W 14u which is supplied to the second input selector 32. The latch pulse signal 14v of the W register 35 is similar to the latch pulse signal 14o of the R register 34, and the signals N ₁ (W) 14t, W. Req 14p, Ø ₂ (14i), and Obtained at Ø ₅ (14k).

By the above-described operation, the address data signals stored in the respective registers 34 to 36 are represented as 12r to 12t, respectively, and specifically designated arbitrarily in the first R cycle period after the SET 12b. The address (N) R is fetched into the R register 34, and the fetched (N) R is selected from the R.SEL (12h) to the address signal 12j from the latch pulse signal 12i to the memory address register 38. It is inputted as " (R) ", which can be led to the address decoder (8) as R address data, and at the same time, the address value can be increased in the increasing circuit (33) and finally fetched into the R register (34). In this method, data of an arbitrarily designated address in the memory cell array can be read one block earlier than in the example of FIG. 11, and the serial data Dout can also output data of an arbitrarily designated address as quickly as one block as shown in FIG. There is a number.

In this case, by providing one block off set in the address value between (N) W and (N) R, the address values of Din and Dout can be made equal at the same point, and the RES 12b is provided. This makes it easy to set the delay amount of Dout.

In the embodiment of FIG. 10, the operation when W. CLK is gated with the CGW will be described using FIG. In FIG. 15, (15a) is CLK, (15b) is CGW, and (15c) is W.CLK obtained by logically multiplying CGW 15b and CLK 15a in the W gate circuit 16 of FIG. (15d) is RES, (15e) is R.Req, (15f) is W.Req, and (15g) is REF.Req.

In this example, CLK is not gated with CGR and R. CLK is equal to CLK 15a. Thus, R.Req 15e and REF.Req 15g are the same in the example of FIG. 12 and the W.Req signal 15f is for example 18 clock pulses of W.CLK 15c following RES 15d, for example. It is obtained at the ratio of. Next, the generation period of the W. Req 15f is delayed compared with the example of FIG. In this case, the phase signal Ø ₀ (15h) is received, and an address cycle signal 15i of each address cycle is generated. The generator of the address cycle signal 15i is shown in FIG. 16 and its operation is shown in FIG. In FIG. 16, reference numerals 185 to 188 denote input signals of the signals Ø ₀ (17d), R.Req (17a), W.Req (17b), and REF.Req (17c) shown in FIG. Output terminals 191 to 193 of the R cycle signal 17h, the W cycle signal 17I, and the REF cycle signal 17j are set / reset flip-flops (hereinafter referred to as SRFF). ), 194 and 195 are inverters, 196 and 197 are AND circuits, 198 to 200 are D flip-flops (hereinafter referred to as DFF), and 201 to 203 are It is an edge detector. The outputs of the SRFFs 191 to 193 are obtained by Q ₁ , Q ₂ , and Q ₃ represented by the signals 17 e to 17 g by Req signals 17 a to 17 c, respectively. Inverters 194 and 195 and AND circuits 196 and 197 provide priorities in the order of Q ₁ , Q ₂ , Q ₃ , and induce them to the D input of each DFF 198, 200. do.

Each D input signal is latched by the Ø ₀ signal 17d at (198) to (200) of the DFF, and the R cycle signal 17h, the W cycle signal 17i, and the REF cycle signal 17j are connected to the Q output. Prepared. The edge detectors 201 to 203 detect, for example, rising edges of the cycle signals 17h to 17j, and detect the detected edge signals 17k to 17o, respectively, to the SRFFs 191 to 193. Induced by the reset input of), resets the output of the SRFF and fetches a new Req signal. By providing the cycle generator 10 configured as described above, each cycle signal is allocated in time division without interfering with each other in time.

By allocating the cycles of the respective addresses in time division, the latch pulse signal 15k of the W.SEL 15j, the memory address register 38, the SEL.R 15o, and the SEL.W 15p are assigned. The latch pulse signals 15g and 15r of the R register 34 and the W register 35 are obtained as shown in Fig. 15, and (15l), (15s), and (15t) by the control signals. The address values of the memory address register 38, the R register 34, and the W register 35 indicated by are obtained. In this case, the data Din 15u is input serially after the RES 15d, so that N (the address value 15l of the memory address register 38 in 18-bit units in synchronization with, for example, W.CLK 15c) is used. Where W) is written to the arbitrarily designated address N (W) of the memory cell array 5, data is transferred to the serial output Dout 15v one block later and arbitrarily assigned the address N (R).

In this manner, W.CLK 15c or R.CLK arbitrarily gated in the CGW signal 15b and the CGR signal is used, and continuous writing of Din 15u and continuous reading of Dout are possible, and the fetched Din is written. There is no inconvenience such as not being turned on or the output Dout not being read.

18 is a modification of the embodiment of FIG. A feature of the modification of FIG. 18 is that the arbitrarily designated address in the SAD register 30 can be selected at once by means of the selector 80 together with the addresses in the registers 34 to 36. The operation of the modification of FIG. 18 will be described in detail with reference to the time chart of FIG.

The configuration of FIG. 18 is similar to the embodiment of FIG. 10 except for the selector 80. In FIG. 19, (19a) is CLK, (19b) is SET, (19c) is R.Req, (19d) is a Ø ₀ signal, and (19e) is a cycle signal for allocating cycles, and FIG. Is the same as 19f to 19j are selection control signals that are guided from the timing generator 26 to the selector 80. For example, the R address arbitrarily specified in the SAD register 30 is selected when the SEL.R (19f) is "high", and the W address arbitrarily specified in the SAD register 30 is selected by the "SEL" W (19g). Is selected when R.SEL (19h) is "high", and the REF address in REF register (36) is selected when REF.SEL (19j) is "high". Each signal selected as above is placed in the memory address register 38 at the timing of the latch pulse signal 19k.

The address value fetched in the memory address register 38 is indicated by the address signal 19l. (19o) to (19q) are latch pulse signals for fetching the address value increased by the increment circuit 33 to each of the registers 34 to 36. FIG. Address data signals of (19r) to (19t) are fetched into the registers 34 to 36.

The operation described above can be performed by an address arbitrarily designated by the fetch of the serial data Din 19u and the output of the serial data Dout 19v as in the operation shown in FIG. A third embodiment shown in FIG. 20 will be described.

The third embodiment differs from the first embodiment shown in FIG. 1 by the purpose of parallel data processing in units of 2 ⁿ (n is a natural number) bits. Therefore, the SP converter 3 and the PS converter 7 are each configured to serially / parallel convert and parallel / serial convert each of 2 ⁿ bits of data, so that the memory cell array 5 comprises (K × 2 ⁿ ) columns × It has an array of m rows (K and m are natural numbers). The address generator 9, the address decoder 8, the input buffer register 4 and the output buffer register 6 are the same as in the embodiment of FIG. 1, and the detailed description thereof is omitted. The address controller 26 'of the third embodiment adds initial setting functions of the W address and the R address to the address controller 26 of the first embodiment, and details thereof will be described.

The address controller 26 'includes an input terminal 11' of a write reset (W.RES) signal, an input terminal 16 of a write clock (W.CLK) signal, and an input terminal 14 of a system clock (CLK) signal. ), An input terminal 15 of the read clock signal R. CLK is provided. The W counter 19 is connected to the terminals 11 'and 16 so that the W.RES and CLK signals are supplied. A W.Req generator 24 and a W. load generator 24 'are connected to the output of the W counter 19 to receive the count value of the W counter 19 to generate a W.Req signal and a W. load signal.

The REF counter 20 counts the system clock signal CLK and the REF.Req generator 25 connected to the output of the REF counter 20 receives the count value of the REF counter 20 and generates a REF.Req signal.

R.RES and R.CLK signals are input to the R counter 17 connected to the terminals 11 and 15. The output of the R counter 17 is connected to the R.Req generator 23 and the R. load generator 23 ', and outputs respective R. load signals and R.Req signals as inputs of the count value of the R counter. .

The W.Req, REF.Req and R.Req signals are input to the cycle generator 10, and the cycle generator 10 generates the W cycle, REF cycle, and R cycle signals and outputs them to the address generator 9 in time division.

In addition, a timing generator 21 for frequency dividing the system clock signal CLK to generate a Ø ₀ to Ø _n phase clock signal is provided.

In the address generator 26 ', the W counter 19 can reset the W.RES signal and the R counter 17 resets the R.RES signal, which is reset to the address generator 9. Supplied.

As with the embodiment of FIG. 1, the W. CLK signal is also supplied to the SP converter 3, the R. CLK signal is also supplied to the PS converter 7, and the W. load signal is input to the input buffer register 4, The R. load signal is supplied to the PS converter 7.

In particular, in the third embodiment, the count values of each of the W counter 19 and the R counter 17 are selected in accordance with the bit conversion amount 2 ⁿ in the SP converter 3 and the PS converter 7.

The operation of the embodiment of FIG. 20 will be described with reference to the time chart of FIG.

In the time chart of FIG. 21, the case of n = 4 and the W.RES signal and R.RES input from the terminals 11 'and 11, as shown by (21b) and (22j) in FIG. The general operation when the set signal is not input is shown.

In Fig. 21, in the address signal 21p, REF, W and R represent the refresh address (REF address), the write address (W address), and the read address (R address), respectively, and M, K, and L respectively. Natural number representing the address value. That is, (M) REF is given a refresh address as a value of M, (K) W is a write address as a value of K, and (L) R is a read address as a value of L. In the data signal 21q of FIG. 21, ^* W denotes a write address (W address) in which 16 bits are written from 0 to 15 of the input data in the data signal 21q, and ^* R is output in the data signal 21r. The read address (R address) where bits from 0 to 15 of the data are read, and the value in parentheses inserted between ^* and W and between ^* and R represents the value of the address.

In FIG. 21, when W. CLK indicated by 21a is input at the terminal 16, the W counter 19 having the count value 2 ⁴ outputs an output pulse signal in the period of count 16 of the W.CLK 21a. (21c) is generated. Similarly, W. load generator 24 'generates output signal W. load 21d in a period of 16 counts and W. Req generator 24 generates output signal W. Req 21e in a period of 16 counts. do. Therefore, receiving the W. load 21d, the SP converter 3 transmits the input data signal Din 21q to the input buffer register 4 in units of 16 bits of 0 to 15 as described. W cycles as shown in the cycle signal 21o in the cycle generator 10 are allocated by the W.Req 21e, and shown in the address signal 21p in the address generator 9 by the W cycle signal. (K) W, (K + 1) W,... In W address is generated and guided to the memory cell array 5 via the address decoder 8. For this W address, parallel data is transferred from the input buffer register 4 to the memory cell array 5 in units of 16 bits. Therefore, the input data 21q at the terminal 1 is expressed in units of 16 bits, for example, ^* (K) W, ^* (K + 1) W, ^* (K + 2) W... Is transferred to the memory cell portion of the memory cell array 5 designated at W address.

On the other hand, the R counter 17 receiving the R.CLK 21i input from the terminal 15 and having the count value 2 ⁴ generates the output pulse signal 21k in a period of 16 counts of the R.CLK 21i. . Similarly, the R. load generator 23 'generates an R. rod 21 l in a period of 16 counts and the R. Req generator generates an R. Req (21m) in a period of 16 counts. In this case, R cycles indicated by cycle generator 10 to 21o are allocated by R.Req 21m, and R addresses indicated by 21p to address generator 9 by this R cycle. L (R), (L + 1) R,... To the memory cell array 5 via the address decoder 8, whereby 16 bits of parallel data corresponding to the R address are transferred from the memory cell array 5 to the output buffer register 6; do. The PS converter 7 receives the R. load 21 l and fetches 16 bits of parallel data transferred to the output buffer register 6. In this case, the data is transmitted to the PS converter 7, and in the units of 16 bits indicated by the output data signal 21r, for example, ^* (L-1) R, ^* (L) R... It reads from the memory cell of the memory cell array 5 designated at the in R address, receives R. CLK, converts it into serial data by the PS converter 7, and outputs it to the terminal 2 as Dout.

The cycle assignment operation by the cycle generator 10 will be described in more detail. The comparison of the cycles assigned with the input W.Req (21e), R.Req (21m) and REF.Req (21h) with the cycle signal 21o is sequential of the request signals inputted in the same period as the cycle is clear. It is assigned according to the occurrence. Therefore, for example, when the signals are input in the order of the W.Req, R.Req, and REF.Req signals, they are allocated simultaneously in the order of W cycle, R cycle, and REF cycle. When the R.Req signal is input in the W cycle processing period, the start of the R cycle is delayed until the W cycle ends. When REF Req is input in the W cycle processing period, the REF cycle is delayed until the end of the R cycle started after the W cycle. In this way, the cycle generator 10 executes allocation of each cycle.

In the third embodiment, as described above, the SP converter 3 is provided on the input side of the memory cell array 5 and the PS converter 7 on the output side, and the SP converter 3 and the PS converter 7 are respectively provided. W counters 19 and R counters 17 corresponding to the conversion bit amounts of? Are separately provided to count W. CLK 21a and R.CLK 21i, respectively, and the respective counter output signals 21c, Each memory cell array 5 and each corresponding to each cycle allocated by time division by W.Req 21e and R.Req 21m of each clock period corresponding to the conversion bit amount using (21k), respectively. Data transfer between the I / O buffer registers 4 and 6, and the I / O buffer registers 4 and 6 and the SP converter 3 and PS by the W. load 21d and R. load 21L. By performing data transfer between the converters 7, simultaneous write / read of the serial data Din 21q and Dout 21r is possible with respect to the video memory.

By selecting the conversion bit amounts of the SP converter 3 and the PS converter 7 from 1 to 2 ⁿ (n is a natural number), the circuit configuration of each of the counters 15 and 17 is simplified.

In the embodiment of Fig. 20, as the input signal of the REF counter 20, a CLK 21f different from the W.CLK 21a and the R.CLK 21i is used to count the output of the CLK 21f. 21g), REF.Req and REF cycles are generated in the same manner as described above, and the REF address is guided to the memory cell array 5 at the time division indicated by 21p to execute the refresh operation for the memory cell array.

The timing generator 21 frequency divides the CLK 21f into, for example, 1/5 to generate signals Ø ₀ to Ø ₄ having different phases for each cycle of the CLK 21f, and as shown in FIG. 21 at 21n. The signal Ø ₀ shown is one of these output signals.

Another example of the FIG. 20 embodiment will be described with reference to the time chart of FIG.

In FIG. 22, n is the same value as the example of FIG. 21 and is the signals 22a to 22r corresponding to the signals 21a to 21r in FIG. The example of FIG. 22 differs from the example of FIG. 21 in that W.RES (21a) and R.RES (21j) do not occur in the example of FIG. 21, whereas R.RES (22j) occurs in the example of FIG. Is the point. This R.RES 22j causes the R counter and the R address to be retained in the address generator 9. As a result, the R counter output signal 22k and the R. rod 22L are initially set in phase of the 16 count period of R. CLK as shown. In addition, although R.Req (22m) is initially set similarly, as shown in FIG. 20, R.Req (22m) is guided by R.RES (22j) to R.Req generator (23). It occurs in synchronization with the RES 22j. The value of the R address in the address generator 9 is also initially set. By R. RES 22j, each cycle signal is allocated as in 22o, and assigned to time division as in each cycle diagram 22p.

In particular, in the third embodiment, the address value assigned by R.Req 22m in synchronization with R.RES 22j is initially set to (O) R as described above, and then (1) R, (2) R... R addresses are given sequentially. According to the R address value, the data signal Dout is output as indicated by (22r). For example, the data of the initial address ^* (O) R is output after 17 counts of the R. CLK 22i after inputting the R.RES (22j). Before the data of the initial address ^* (O) R is derived, the data of the previous address ^* (L-1) R is successively output in 16 bits and sequentially, and the last 16 bits are stored in the data. It is held in a held state.

In this method, by providing means (not shown) for specifying the R.RES 22j externally, the R counter 17 is reset by the R.RES 22j, and the address is initially set by R.RES 22j. After inputting .RES (22j), it is possible to specify that the data of the initial setting address (e.g., ^* (O) R) is output in some R.CLK. The R.RES 22j is input by resetting the counter 17 by the R.RES 22j and initializing the phases of the generation cycles of the R. rod 22L and the R.Req 22m. The transfer of parallel data from the new output buffer register 6 to the PS converter 7 is prevented from later until the data of the initial set R address ( ^* (O) R) is directed to the output, for example as shown in (22r), ^* the R (L-1) after the 16-bit data of R is the output in series ^* in between until the output data of the R (O) (L-1 ) It is possible to hold the last data. In this case, by inputting R.RES 22j in the blanking period without changing the amplitude of the video signal, for example, the blanking period is held, thereby preventing inconvenience caused by the loss of bits of the output data Dout. .

In general, a delay of 262 or 263 lines as one frame delay is obtained by using a video memory including an input stage of an SP transform and an output stage of a PS transform having a 1 to 2 ⁿ bit conversion amount, or one frame delay of 525 lines. When four times the color carrier frequency fsc is selected as the clock frequency, one line becomes 910 clocks, and at a delay of 262, 263, or 525 lines, it is generally not divided by 2 _n . Loss occurs. However, according to this embodiment, the inconvenience caused by this loss can be eliminated by doing the above.

Another example of the operation of the embodiment of FIG. 20 will be described with reference to the time chart of FIG.

In FIG. 23, n is the same value as in the example of FIG. 21, and the signals 23a to 23r correspond to the signals 21a to 21r in FIG. Compared to the example of FIG. 21 or the example of FIG. 22, R.RES (23k) and W.RES (23b) both occur in the example of FIG. The R counter output 23k, R. rod 23L and R.Req 23m by R.RES 23j allocate R addresses and provide Dout 23r in the same manner as in the example of FIG. . On the other hand, when the W counter 19 is reset by the W.RES 23b, the period during which the W counter output signal 23c, the W load signal 23d, and the W. Req signal 23e are generated is the 23rd time. As shown in the figure, it is initially set by the W.RES 23b. The W.Req 23e is generated at the 17th count of the W.CLK 23a, for example, after the W.RES 23b is input. The value of the W address in the address generator 9 also initially sets the W.RES 23b. Thus, each W cycle signal is assigned as shown by 23o and each W address is assigned as shown by 23p. As a result, for example, the W address where the serial data Din is initially set in 16-bit units after the input of the W.RES 23b. Sequentially in * (O) W^*(1) W,^*(2) W… The low light is written into the memory cell array 5. Therefore, by using the W.RES 23b, it is possible to specify that the Din is written at the address initially set in the memory cell array 5. In addition, by using W.RES 23b and R.RES 23j, the delay time of data can be arbitrarily determined outside the memory.

The W counter 19, W. rod generator 24 'and W. Req generator 24 used in the embodiment of FIG. 20 are specifically configured as shown in FIG. 24 and used in the embodiment of FIG. The R counter 17, the R. rod generator 23 'and the R. Req generator 23 are specifically shown in FIG.

In Figures 24 and 25, 204-210 are inverters, 211-218 are counters, 219 and 220 are flip-flops for latching, 221 and 222 Is an AND circuit, and 223 is a NAND circuit, and the other elements are the same as in FIG.

In FIG. 24, W. CLK at terminal 16 is counted by 4-bit counters 211-214 and flips a counter output pulse signal generated in a period of 16 pulses of W. CLK, for example. The W.Req signal latched by the flop 219 shown in the time charts of FIGS. 21 to 23 can be obtained. The count output pulse signal is logically multiplied by W. CLK at the AND gate 221 to generate the W. load signal shown in the time charts of Figs. In the configuration of FIG. 24, the W counter 19 can easily reset the W.RES input at the terminal 11 '.

In the above description, it can be easily inferred that the R. Req and R. rods shown in FIGS. 21 to 23 are obtained by the configuration of FIG.

FIG. 26 shows a modification of the embodiment of FIG.

This modification differs from the embodiment of FIG. 20 in that the SP converter 3 is provided with an input terminal of the memory cell array 5. In the embodiment of FIG. 20, a shift register is generally used. The input buffer registers 104 and 105 are used to use the SP conversion of the input data signal Din. Similarly, the PS change of the output stage is also executed by the two output buffer registers 106 and 107.

The operation of the modification of FIG. 26 will be described.

In a variant, the input registers 104 and 105 and the output registers 106 and 107 are 2 ⁿ bit registers. The serial data Din at the terminal 1 is first written consecutively in the first input register 104 by 2 ⁿ bits, for example, and then written in the second input register 105. In the period for writing to the second input register 105, the data of the first input register 104 is transferred to the memory cell array 5 as 2 ⁿ bits of parallel data. Thereafter, when writing of 2 ⁿ bits in the second input register 105 ends, writing in the first input register 104 is started again, and the data of the second input register 105 is changed to 2 ⁿ bits within that period. The data is transferred into the memory cell array 5 as parallel data.

As a result, two sets of bits of the input data signal Din at the terminal 1 are fetched in succession into the two input registers 104 and 105, respectively, and the data of one input register is stored in the memory cell array 5. The new Din is prevented from being fetched into the input register before being transferred to the input register, and is completely transferred from the input register to the memory cell array 5.

In the above operation, similarly to the embodiment of FIG. 20, the address data of the 2 ⁿ W counter 19 is decoded by the input register address decoder 102, and in which address in the register, the Din at the terminal 1 is written. Are sequentially assigned, and the Din at the terminal 1 is input to the first and second inputs by a signal obtained by dividing the count output of the W counter 19 by 1/2 frequency in the 1/2 frequency divider 100. It designates where register is derived and designates which register data is transferred to the memory cell array 5.

Two output registers 106 and 107 and an output register address decoder 103 are provided at the output stage to operate sequentially in the same manner as the input registers 104 and 105 and the input register address decoder 102. Therefore, 2 ⁿ bits of parallel data are transferred from the memory cell array 5 to the second register 107 within a period in which data of the first output register 106 is derived as the serial data Dout at the terminal 2. . When the 2 ^n- bit serial conversion of the data of the first output register 106 ends, the serial conversion of the data of the second output register 107 is started, and the first memory register 5 is newly updated in the memory cell array 5. 2 ⁿ bits of parallel data are transferred to the output register 106.

By using the switches of the first and second output registers 106 and 107, the output signal of the R counter 17 that counts 2 ⁿ is halved by the half frequency divider 103. Executed by the divided signal.

The other operations are the same as those in FIG. 20, and output data can be obtained as in the case of FIG.

In the embodiment of Figs. 20 to 26, the bit conversion amount of 1 to 2 ⁿ has been described in the case of 1 to 16, but the present invention is not limited to 1 to 16 but may be 1 to 8 or 1 to 32.

In the third embodiment, data is handled in units of 2 ⁿ bits and used as a digital memory such as a facsimile.

In the above-described embodiment, since the memory cells use DRAMs, a refresh signal generation mechanism is required, but can be eliminated by using a static memory.

Claims (12)

A serial / parallel converter 3 for converting serial input data into parallel data, first holding means 4 for holding the parallel data from the serial / parallel converter, and parallel data output from the first holding means. Data storage means (5) for storing the data; second holding means (6) for holding parallel data read from the data storage means; and parallel / converting parallel data read from the second holding means to serial data. A serial converter 7, an address generator 9 for supplying write and read addresses to the data storage means in time division and first and second gate means 15 for differently gated at least a master clock with at least two pulses; 16) first and second counters 17 and 19 for counting the read clock signal and the write clock signal outputted from the two gate means, respectively, and to the count output signal of the first counter. A read request generator 23 for generating a read request signal in response thereto and a write request generator 24 for generating a write request signal in response to the count output signal of the second counter 19, wherein the address generator 9 And a read clock signal obtained by the first gate means 15 is used as a clock signal for serially transferring data fetched in parallel in the parallel / serial converter, And the write clock signal obtained by the second gate means is used as a clock signal for sequentially transferring data fetched in the serial / parallel converter to the first holding means. The method of claim 1, wherein the address controller 26 further includes a third counter 18 for counting master clock signals and corresponding to the count output signals of the first and third counters. And the read request generator 23 generates a read request signal. The cycle of claim 1, wherein the address controller 26 further inputs the read request signal and the write request signal to output the read cycle and the write cycle time-divided in a predetermined priority order to the address generator. An image memory comprising a generator (10). 4. The refresh controller according to claim 3, wherein the address controller 26 outputs a refresh signal in response to a fourth counter 20 for counting a master clock signal and a count output signal from the fourth counter. A request generator 25, wherein the cycle generator inputs the refresh signal to output time-division read cycles, write cycles, and refresh cycles to the address generator, and the first and second holding means And at least the write request signal and read request signal are generated during one cycle until the parallel data is held and the held parallel data is output. The method according to claim 1, wherein the read request generator 23 indirectly outputs the read request signal regardless of the first counter and the third counter in response to an input of a reset signal. And outputting said read request signal in response to an output signal of said third counter, and thereafter generating said read request signal in response to a periodic count output signal from said first counter. 2. The address generator (9) according to claim 1, wherein the address generator (9) stores an arbitrary address register (30) for fetching an externally specified arbitrary address, a read address register (34) for storing a read address, and a write address. A write address register 35, an output selector 37 which selects an address from one of the registers and outputs the selected address, and stores an address output from the output selector and outputs the address according to a predetermined clock signal A memory address register 38, an address increasing / decreasing means 33 for inputting the address to an increased / decreased address, and an arbitrary address of the arbitrary address register and an output signal of the address increasing / decreasing means, and selecting the read register and First inputting the selected signals to the write registers respectively And second input selectors (31, 32). 7. The cycle generator (10) according to claim 6, wherein the address generator (9) is configured such that when the read control signal is a read address selection signal and a read latch signal, and the write control signal is a write address selection signal and a write latch signal. When a read control signal and a write control signal are inputted, a random address received from the random address register is fetched into the read address register and the write address register, and the output selector 37 writes the read control signal and the write control signal. Time-dividing the read address and write address in response to an output of the first input selector and the read address register are controlled by the read control signal, and the second input selector and the write address register are the write control signal. Video memo controlled by . 10. The fourth counter of claim 9, wherein the address controller 26 further comprises a fourth counter 20 for counting a mast clock signal and the fourth counter when the refresh control signal is a refresh latch signal and a refresh register selection signal. And a refresh request generator (25) for generating a refresh control signal in accordance with a count value of?, Wherein said address generator further comprises a refresh address register (36) which operates on said refresh control signal. The method according to claim 1, wherein the series / parallel converter 3, the parallel / serial converter 7, the first holding means 4, and the second holding means 6 are 2 ⁿ (n is Handles parallel data in units of bits, and the data storage means 5 is a memory cell array having (K × 2 ⁿ ) columns × m rows (K, m is a natural number), and the address controller 26 is respectively First and second counters 19 and 17 for counting different clock signals, and the write for outputting a write request signal each time the first counter counts a pulse (L × 2 ⁿ ) (L is a natural number); an image memory comprising a request generator 24, the read request generator (23) for the second counter outputs a read request signal each time the count pulses (J is a natural number) (J 2 × ⁿ⁾ of the. 10. The apparatus according to claim 9, wherein the address controller 26 further includes reset means for resetting the first and second counters independently from each other and the write address generated from the address generator or And an initial setting means for initially setting an address value of a read address. In the claims, claim 10, wherein when said first counter is in the counting pulse of the read clock signal (J × 2 ⁿ⁾ reset by said reset means before counting the second pulse of the first In synchronization with the reset of the counter, the cycle generator allocates a new read cycle corresponding to the memory cell array, outputs all of the converted data bits at the reset in the parallel / serial converter and then the first A video memory which repeatedly outputs the last data bit output until the next signal is output from the counter and the parallel data held in the second holding means is newly induced in the parallel / serial converter. The video memory according to claim 1, wherein each of the first and second holding means includes two holding means (104, 105, 106, 107) connected in parallel to alternately perform input and output of data.

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