KR910009610U - 부트 스트랩핑 데이타 출력회로 - Google Patents

부트 스트랩핑 데이타 출력회로

Info

Publication number
KR910009610U
KR910009610U KR2019890017102U KR890017102U KR910009610U KR 910009610 U KR910009610 U KR 910009610U KR 2019890017102 U KR2019890017102 U KR 2019890017102U KR 890017102 U KR890017102 U KR 890017102U KR 910009610 U KR910009610 U KR 910009610U
Authority
KR
South Korea
Prior art keywords
output circuit
data output
bootstrap data
bootstrap
circuit
Prior art date
Application number
KR2019890017102U
Other languages
English (en)
Other versions
KR940006659Y1 (ko
Inventor
정원화
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019890017102U priority Critical patent/KR940006659Y1/ko
Publication of KR910009610U publication Critical patent/KR910009610U/ko
Application granted granted Critical
Publication of KR940006659Y1 publication Critical patent/KR940006659Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR2019890017102U 1989-11-18 1989-11-18 부트 스트랩핑 데이타 출력회로 KR940006659Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890017102U KR940006659Y1 (ko) 1989-11-18 1989-11-18 부트 스트랩핑 데이타 출력회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890017102U KR940006659Y1 (ko) 1989-11-18 1989-11-18 부트 스트랩핑 데이타 출력회로

Publications (2)

Publication Number Publication Date
KR910009610U true KR910009610U (ko) 1991-06-29
KR940006659Y1 KR940006659Y1 (ko) 1994-09-28

Family

ID=19291996

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019890017102U KR940006659Y1 (ko) 1989-11-18 1989-11-18 부트 스트랩핑 데이타 출력회로

Country Status (1)

Country Link
KR (1) KR940006659Y1 (ko)

Also Published As

Publication number Publication date
KR940006659Y1 (ko) 1994-09-28

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