KR910009051A - Video signal level limit circuit - Google Patents

Video signal level limit circuit Download PDF

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Publication number
KR910009051A
KR910009051A KR1019890014202A KR890014202A KR910009051A KR 910009051 A KR910009051 A KR 910009051A KR 1019890014202 A KR1019890014202 A KR 1019890014202A KR 890014202 A KR890014202 A KR 890014202A KR 910009051 A KR910009051 A KR 910009051A
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KR
South Korea
Prior art keywords
signal
video signal
signal level
limit circuit
level limit
Prior art date
Application number
KR1019890014202A
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Korean (ko)
Other versions
KR920009606B1 (en
Inventor
박영준
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890014202A priority Critical patent/KR920009606B1/en
Publication of KR910009051A publication Critical patent/KR910009051A/en
Application granted granted Critical
Publication of KR920009606B1 publication Critical patent/KR920009606B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Picture Signal Circuits (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음No content

Description

영상신호 레벨 제한회로Video signal level limit circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 일반적인 영상신호 표시회로도.1 is a general video signal display circuit diagram.

제2도는 디지탈신호 처리부(12)를 갖는 영상신호 표시회로도.2 is a video signal display circuit diagram having a digital signal processor 12. FIG.

제3도는 표준 NTSC신호 파형도.3 is a waveform diagram of a standard NTSC signal.

Claims (2)

디지탈신호 처리부를 갖는 영상신호 표시회로에 있어서, 상기 디지탈신호 처리부를 통해 디지털신호 처리가 된 영상신호(VS)와 제한신호(LS)를 비교 출력하는 비교기(20)와, 제어신호(CS)에 의해 스위칭하여 영상신호(VS)와 제한신호(LS)를 선택 출력하는 스위치수단과, 상기 비교기(20)의 출력신호와 블랭킹펄스(BP)를 논리연산하여 상기 스위치수단의 스위칭을 제어하는 제어신호(CS)를 발생하는 게이트 수단으로 구성함을 특징으로 하는 영상신호 레벨 제한회로.A video signal display circuit having a digital signal processor, comprising: a comparator 20 for comparing and outputting a video signal VS and a limit signal LS subjected to digital signal processing through the digital signal processor; and a control signal CS. A switch means for switching and outputting the image signal VS and the limit signal LS, and a control signal for controlling the switching of the switch means by performing a logical operation on the output signal and the blanking pulse BP of the comparator 20. And a gate means for generating (CS). 제1항에 있어서, 영상신호(VS)의 데이터가 n비트인 경우 제한신호(LS) 데이터 레벨 X는 2n/4≥x≥0임을 특징으로 하는 영상신호 레벨 제한회로.2. The video signal level limiting circuit according to claim 1, wherein the limit signal (LS) data level X is 2 n / 4? X? 0 when the data of the video signal VS is n bits. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: It is to be disclosed based on the initial application.
KR1019890014202A 1989-10-04 1989-10-04 Video signal level limit circuit KR920009606B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890014202A KR920009606B1 (en) 1989-10-04 1989-10-04 Video signal level limit circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890014202A KR920009606B1 (en) 1989-10-04 1989-10-04 Video signal level limit circuit

Publications (2)

Publication Number Publication Date
KR910009051A true KR910009051A (en) 1991-05-31
KR920009606B1 KR920009606B1 (en) 1992-10-21

Family

ID=19290407

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890014202A KR920009606B1 (en) 1989-10-04 1989-10-04 Video signal level limit circuit

Country Status (1)

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KR (1) KR920009606B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960040364A (en) * 1995-05-16 1996-12-17 유충식 Pharmaceutical composition containing taurine and penem or carbapenem derivatives

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960040364A (en) * 1995-05-16 1996-12-17 유충식 Pharmaceutical composition containing taurine and penem or carbapenem derivatives

Also Published As

Publication number Publication date
KR920009606B1 (en) 1992-10-21

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