KR910008870A - Protection circuit of semiconductor chip - Google Patents

Protection circuit of semiconductor chip Download PDF

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Publication number
KR910008870A
KR910008870A KR1019890014928A KR890014928A KR910008870A KR 910008870 A KR910008870 A KR 910008870A KR 1019890014928 A KR1019890014928 A KR 1019890014928A KR 890014928 A KR890014928 A KR 890014928A KR 910008870 A KR910008870 A KR 910008870A
Authority
KR
South Korea
Prior art keywords
protection circuit
circuit
protection
semiconductor chip
vcc
Prior art date
Application number
KR1019890014928A
Other languages
Korean (ko)
Other versions
KR920004338B1 (en
Inventor
장득수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890014928A priority Critical patent/KR920004338B1/en
Publication of KR910008870A publication Critical patent/KR910008870A/en
Application granted granted Critical
Publication of KR920004338B1 publication Critical patent/KR920004338B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 칩의 보호회로Protection circuit of semiconductor chip

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 실시예를 나타낸 블럭다이어그램도4 is a block diagram showing an embodiment of the present invention.

제5도는 본 발명의 실시 회로도5 is an implementation circuit diagram of the present invention.

제6도는 본 발명의 반도체 칩 내에서 나타나는 전류 대 전원 특성곡선도이다.6 is a curve of current versus power characteristics appearing in the semiconductor chip of the present invention.

Claims (5)

입력단자(IN) 및 내부회로(4) 사이에 구성되어 발생되는 과전압 또는 정전기를 방전시키는 입력보호수단과, 출력단자(OUT) 및 내부회로(4) 사이에 구성되어 발생되는 과전압 또는 정전기를 방전시키는 출력보호수단과, 내부회로(4)의 전원(VCC)측 및 접지(GND)측 사이에 구성되어 발생되는 과전압 또는 정전기를 방전시키는 파워보호수단과, 를 포함하는 반도체칩의 보호회로.Input protection means for discharging overvoltage or static electricity generated between the input terminal IN and the internal circuit 4, and discharging overvoltage or static electricity generated between the output terminal OUT and the internal circuit 4 And power protection means for discharging overvoltage or static electricity generated between the power supply (VCC) side and the ground (GND) side of the internal circuit (4). 제1항에 있어서 입력보호수단을 구성하는 입력보호회로(1)는 펀치스루 MOS 트랜지스터(MPT1), (MPT2)로 구성되는 제1보호회로(1-1)와, 다이오드(D1),(D2)로 구성되는 제2보호회로(1-2)와,로 구성되는 반도체칩의 보호회로.The input protection circuit 1 constituting the input protection means of claim 1 comprises a first protection circuit 1-1 composed of punch-through MOS transistors MPT1, MPT2, diodes D1, D2. A second protection circuit (1-2) composed of a circuit board), and a protection circuit of a semiconductor chip composed of: 제1항에 있어서 출력보호수단을 구성하는 출력보호회로(2)는 펀치스루 MOS 트랜지스터(MPT3), (MPT4)로 구성되는 제1보호회로(2-1)와, 다이오드(D3),(D4)로 구성되는 제2보호회로(2-2)와,로 구성되는 반도체칩의 보호회로.The output protection circuit (2) constituting the output protection means according to claim 1 comprises a first protection circuit (2-1) composed of punch-through MOS transistors (MPT3), (MPT4), diodes (D3), (D4). A second protection circuit (2-2) consisting of a) and a protection circuit of a semiconductor chip consisting of. 제1항에 있어서 내부회로(4)의 전원(VCC)측 및 접지(GND)측 사이에 구성되는 파워보호회로(3)는 전류제한 저항(RP) 및 제너다이오드(DZ1),(DZ2)로 구성시켜된 반도체칩의 보호회로.The power protection circuit (3) according to claim 1, which is configured between the power supply (VCC) side and the ground (GND) side of the internal circuit (4), is a current limiting resistor (RP) and a zener diode (DZ1), (DZ2). A protective circuit of a semiconductor chip constructed. 제1항 또는 제4항에 있어서 파워보호회로(3)가 트리거되는 보호범위는 전원(VCC)의 최대값이상 및 SCR의 트리거전압(VBS) 이하로 동작되게한 반도체칩의 보호회로.The protection circuit of a semiconductor chip according to claim 1 or 4, wherein the protection range in which the power protection circuit (3) is triggered is operated below a maximum value of a power supply (VCC) and below a trigger voltage (VBS) of an SCR. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890014928A 1989-10-17 1989-10-17 Semiconductor chip protection circuit KR920004338B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890014928A KR920004338B1 (en) 1989-10-17 1989-10-17 Semiconductor chip protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890014928A KR920004338B1 (en) 1989-10-17 1989-10-17 Semiconductor chip protection circuit

Publications (2)

Publication Number Publication Date
KR910008870A true KR910008870A (en) 1991-05-31
KR920004338B1 KR920004338B1 (en) 1992-06-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890014928A KR920004338B1 (en) 1989-10-17 1989-10-17 Semiconductor chip protection circuit

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KR (1) KR920004338B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3899984B2 (en) * 2002-04-09 2007-03-28 富士電機デバイステクノロジー株式会社 Overvoltage protection circuit
KR100689743B1 (en) 2004-10-01 2007-03-08 삼성전자주식회사 Electro Static Discharge Protection and Input Impedance Matching Circuit for Low Noise Amplifier And Low Noise Amplifier

Also Published As

Publication number Publication date
KR920004338B1 (en) 1992-06-01

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