KR910006975B1 - Conductive plug for contacts and vias on intergrated circuits - Google Patents

Abstract

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Description

[Name of invention]

How to Charge Contacts and Vias on Integrated Circuits with Conductive Plugs

[Brief Description of Drawings]

The advantages and features of the present invention described will be readily apparent to those skilled in the art upon reading the following detailed description with reference to the accompanying drawings.

1a-d are schematic illustrations of one embodiment of the method of the invention,

Figures 2a-c schematically show another embodiment of the method of the present invention,

3a-d schematically illustrate another embodiment of the method of the invention,

Figures 4a-e schematically illustrate another embodiment of the method of the present invention,

5a-e show yet another embodiment of the method of the present invention.

Detailed description of the invention

[Background of invention]

The invention described relates to a technique for providing a conductive path between a device and a metallization layer or between metallization layers of an integrated circuit, in particular a conductive plug for interconnecting the metallization layer of the device and the integrated circuit. It relates to a technique for forming a conductive plug.

In integrated circuits, devices or devices formed within a substrate are interconnected with metal (eg, aluminum) leads that are typically formed by a continuous process of masking and deposition.

The masking and deposition process is called metallization and generally provides a metallization layer on top of the insulating oxide or glass layer. The insulating oxide or glass on which the metallization layer is deposited is generally used for (a) metallization contacts to silicon or polysilicon, or (b) openings to form metallization vias to other metallization layers, or It includes a window.

However, according to known metallization techniques, contacts and via openings or windows must be selectively disposed for two and three metallization layers. This choice is required due to the limitations of photolithographic and deposition processes.

Known metallization techniques include planarized and non-planarized processes. As used herein. The plannerization process is to smooth the surface of the insulating layer before deposition of metal. The planarization surface may comprise a nearly continuous planar surface or may comprise other levels of planar regions. In either case, the top surface of the insulating layer is smoothed.

In particular, the non-planarization process allows only one opening through a given area. In other words, only one layer has an opening through a given area. In addition, the openings should be at least a predetermined distance from the other openings. The actual distance depends on whether the adjacent opening is in the immediately adjacent oxide layer.

According to the plannerization process, the restriction is not strict. There may be more than one opening through a given region unless the opening is on an adjacent oxide layer. However, due to process limitations, the top of the metal deposited through the openings includes an indentation and minimal space is required between adjacent openings. The need for this space is less stringent than for non-planarization processes.

As a result of design rules relating to known metallization layer non-planning and planarization processes, routing becomes inherently complex and difficult. This design rule also limits device density, but achieves greater density with the planarization process as compared to non-planarization processes.

Another consideration of known processes for metallization contacts and vias is the limitation of the minimum size of the openings. In particular, if the opening is made too small, the metallization layer deposited on the edge of the opening may become too thin and crack. The limitation of the minimum opening size also adversely affects the device density.

[Summary of invention]

Therefore, it is advantageous to provide conductive filled integrated circuit structure contacts and via openings that give flexibility in the location of openings on one oxide layer relative to the location of other openings on adjacent oxide layers.

It is also advantageous to provide conductively charged integrated circuit structure contacts and via openings that allow for effective routing.

Another advantage is to provide a small size of conductively charged integrated circuit structure contacts and via openings.

Another advantage is to provide conductively charged integrated circuit structure contacts and via openings that allow for high density of the device.

Another advantage is to provide planarized conductively charged integrated circuit structure contacts and via openings.

The above and other advantages are provided by the present invention in a method for filling contacts and via openings in an integrated circuit with conductive plugs. The method comprises (a) forming one or more openings in the planarization oxide layer, each disposed and exposed on a semi-insulating or conductive region, and (b) adjacent surfaces of the oxide layer to form respective planarization conductive plugs. Filling the at least one opening with the conductive material to approximately the same level as.

Another aspect of the invention is to (a) form one or more first openings each disposed and exposed on an associated semi-insulating or conductive region to a first predetermined depth in the planarizing oxide layer, and (b) Partially filling one or more first openings with a conductive material at a level corresponding to the selected depth of two, and (c) planarizing the one or more second openings respectively disposed and exposed on the associated semi-insulating or conductive region. Forming a second predetermined depth in the oxide oxide layer, and (d) filling one or more first and second openings at approximately the same level to form respective planarization plugs in the openings. It is about.

In the following detailed description and the various drawings, like elements are designated by like reference numerals.

Referring now to FIG. 1A, openings 11 and 13 of different depths are formed in the planarization oxide layer 15, for example by appropriate masking and etching. The side surfaces of the openings 11 and 13 are vertical, and the lower portion of the opening and the area between the openings 11 and 13 and the upper portion of the adjacent region are horizontal. The openings 11 and 13 are preferably of the same diameter.

[details]

The oxide layer 15 is shown formed on a thin gate oxide layer 16 that is incorporated into a thick field oxide layer 21. Gate oxide 16 and field oxide 21 are formed on substrate 17. The opening 11 exposes a portion of the substrate 17 and the opening 13 exposes a portion of the polysilicon layer 19 formed on the field oxide 21. Part of the substrate 17 exposed by the opening 11 can be part of the doped region of the device, and the polysilicon layer 19 can form the gate of the device.

For ease of understanding, another embodiment of the present invention is shown to include a gate oxide layer 16, a substrate 17, a polysilicon layer 19 and a field oxide 21 shown in FIG. However, these structures are not shown in the respective figures. Although the description herein is mainly described with respect to openings for silicon contacts for ease of understanding, it should be understood that the present invention is not limited thereto and is applicable to openings for vias interconnecting metallization layers.

Poly or amorphous silicon is chemically deposited on the structure of FIG. 1a to provide a thin (about 100 microns to 1000 microns) deposited silicon blanket layer 23 as shown in FIG. 1b. The structure of FIG. 1B is then anisotropic silicon etched to remove the deposited silicon layer 23 from the horizontal surface of the structure, leaving a considerable amount of deposited silicon layer 23 on the vertical surface. It is appropriate to over-etch so that the silicon layer 23 deposited in the top of the openings 11 and 13 is removed to generate the structure of FIG. 1C. Over-etching suppresses overfilling of openings 11 and 13 with tungsten that is selectively deposited in the next step.

After the step of anisotropic etching, tungsten is deposited by chemical vapor deposition. Since tungsten is selectively deposited on silicon and metal, chemically deposited tungsten is deposited only on the silicon under the openings 11, 13 and on the silicon layer 23 deposited on the sides of the openings 11, 13. Since tungsten is deposited on the metal, tungsten is also suitably deposited for via openings in the metallization layer.

The deposition of tungsten is controlled to provide deposited planarized tungsten plugs 25, 27 filling the openings 11, 13 as shown in FIG. Optimally, only the top of the final tungsten plugs 25, 27 should be slightly higher than the surrounding horizontal surface so that the top of the structure remains planarized.

The tungsten plugs 25 and 27 in FIG. 1d include a vertically located vertical boundary that schematically illustrates the merging state of the suitable deposition growth of tungsten. Another embodiment of the present invention is also schematically shown with vertical boundaries in the deposited region for the same reason. It should be noted that this boundary eventually stops so that when the deposited structure is subjected to another heating process, it can be identified.

Referring to FIGS. 2A-2C, another technique according to the present invention for metallizing vias or contact openings that are of different depths and can be of different diameters is shown. Each opening expected by this technique has a lower portion of silicon or metal as described above in connection with FIGS. 1A-1D.

2A illustrates a structure having openings 111 in the planarization oxide layer 115. For example, opening 111 is formed by appropriate masking and etching. Subsequent processing results in the formation of a shallow opening 113, the next location of which is shown in dashed lines. Tungsten is then chemically deposited to cause opening 111 to be filled from below. Tungsten chemical vapor deposition is controlled to provide a tungsten plug 125 such that the depth of the partially filled opening 111 is equal to the expected depth of the next opening 113 as shown in FIG. 2B.

An opening 113 is then formed, for example, by masking and etching, and then tungsten is chemically deposited. Following this deposition, openings 111 and 113 are filled with deposited planarized tungsten plugs 125 and 127. Chemical vapor deposition is controlled so that the tops of the deposited tungsten plugs 125, 127 are slightly higher than the surrounding horizontal surface so that the tops of the structures remain flattened. The final structure is shown in Figure 2c.

The techniques shown in FIGS. 2A-2C can be usefully used in applications where the depth and diameter of the contacts or via openings vary greatly. This technique uses a specific mask and etching process for each contact or via opening of a given depth, followed by chemical deposition of tungsten.

The use of separate masks, etching and partial filling steps for openings of different depths and diameters, as described above, allows more precise control of the size and depth of the openings by using separate masks, thereby providing more precise control than previous layers. It is well aligned.

For example, alignment registration can be improved by about 40%. Partial filling of the deeper openings can also provide a more flattened plug since the openings are all uniformly filled from the bottom. As mentioned above, the openings 111 and 113 can be of different diameters, providing a planarized plug as the openings are filled from below.

Referring now to FIGS. 3A-3D, another technique envisioned by the present invention for providing planarized conductively filled contacts and via openings is shown. According to this technique, openings 211 and 213 of the same diameter, which can be of different depths, are formed in the planarized oxide layer 215 (eg by masking and etching). According to another technique contemplated by the present invention, the lower portions of the openings 211 and 213 may be silicon or metal. The final structure is shown in Figure 3a.

Then, the selected material onto which tungsten is deposited is chemically deposited on the structure of FIG. 3a to provide a thin (100 ns-1000 ns) deposited blanket layer of this selected material, as shown in FIG. 3b. These materials include refractory metal silicides or silicon, titanium nitride, titanium, tungsten disilicides, titanium-tungsten alloys, tungsten nitrides, or others on which tungsten is deposited. There is another substance.

Tungsten is then chemically deposited on the structure, and the deposited layer 229 acts as an adhesive layer of tungsten. In particular, the contact or via openings 211, 213 are filled from the side, and the final structure fills the openings 211, 213 and extends upwardly from the top of the openings 211, 213 as shown in FIG. 3C. ).

The structure of FIG. 3C is then etched uniformly until only tungsten remains in the contacts and via openings 211,213. The final structure includes tungsten plugs 225 and 227 planarized in openings 211 and 213, as shown in FIG. 3D.

Referring now to FIGS. 4A-4E, a technique contemplated by the present invention for filling a contact or via opening with a doped polysilicon plug is shown. Openings 311 and 313 of the same diameter, which can be of different depths, are formed in the oxide layer 315. The final structure is shown in Figure 4a. The selected material is chemically deposited or sputtered onto the structure of FIG. 4A to provide a thin (100 μs-1000 μs) blanket deposition layer 329, as shown in FIG. 4B. The selected material acts as a diffusion barrier and can be composed of refractory metal silicides, titanium, titanium tungsten, titanium nitride, or tungsten nitride. The final structure of this deposition material is shown in Figure 4b. The deposition material may also be tungsten, in the case of tungsten the final structure is different from that of other materials and will be described with reference to FIGS. 5A-5E.

Referring to 4B, a deposition layer 329 of a material other than tungsten is covered on the horizontal and vertical surfaces of the structure. Then, silicon is chemically deposited to provide the deposited polysilicon layer 331 as shown in FIG. 4C. The deposited polysilicon layer 331 fills the openings 311 and 313 and extends upwardly from the top of this opening. The deposited polysilicon layer 331 is then doped by ion implantation as shown in FIG. 4d. The doped polysilicon is activated by heating, and the structure is then etched to provide planarized dope silicon plugs 325 and 327 in openings 311 and 313 as shown in FIG. 4E.

Referring now to FIGS. 5A-5E, another technique is envisioned by the present invention for filling contact or via openings with doped polysilicon plugs and shown using tungsten as a diffusion barrier. Openings 411 and 413 of the same diameter, which can be of different depths, are formed in the oxide layer 415 by, for example, masking and etching, as shown in FIG. 5A. Tungsten is chemically deposited and selectively deposited under the openings 411 and 413 because the bottom of the openings 411 and 413 is silicon or metal. Deposition is controlled to provide a thinly deposited tungsten layer 429 below the openings 411 and 413 as shown in FIG. 5B. Silicon is then deposited by chemical vapor deposition to generate the structure of FIG. 5d including the deposited polysilicon layer 431. The deposited polysilicon layer 431 fills the openings 411 and 413 and extends upwardly from the top of the openings.

The deposited polysilicon 431 is then doped by ion implantation, as shown in FIG. 5D. The doped polysilicon is activated by heating, and the structure is etched to provide the structure of FIG. 5E including the planarized polysilicon plug in the openings 411 and 413.

The method shown in FIGS. 5A-5E is rather simple so that only the etching needed to planarize the plug in the opening should be etched through one type of material.

It should be noted that the techniques of FIGS. 4A-4E and 5A-5E are only suitable for filling (a) contact openings and (b) via openings with hot metal. This is due to the high temperatures required for the deposition of polysilicon.

According to the techniques of FIGS. 4A-4E and 5A-5E, the deposited diffusion barrier layer is only necessary if the opening is a contact opening. When this technique is used for via openings, no barrier is needed, and the step of chemically depositing the barrier layer is unnecessary. However, as already noted, the metal (eg tungsten) underneath the via opening must have a sufficiently high melting temperature so that it does not melt when silicon is deposited.

The technique described above describes techniques for using tungsten to selectively deposit on certain metals, such as metals and silicon, but other conductive materials, such as molybdenum, which are selectively deposited may also be used.

In addition, the present invention is not limited to the openings of silicon or metal, and generally expects openings of suitable semi-insulating or conductive regions.

The above description describes a technique for providing a conductive plug for filling contact openings and via openings. This conductive plug provides planarized contacts and vias, thus freely providing the location of the contacts and via openings. As a result of this positional freedom, interconnect routing is simplified. Also, as a result of the conductive plug formation, the via openings can be made small. In addition, the use of a conductive plug can further narrow the gap between the opening and the via opening. In addition, the technique for providing conductive plugs further facilitates the use of multilayer metallization. As a result of the free opening position, the spacing between the openings can be reduced, the opening size can be reduced, and the device density can be large.

While specific embodiments of the present invention have been described and illustrated, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope and principles of the invention as defined in the following claims.

Claims (24)

A method for filling a contact or via opening in an integrated circuit with a conductive plug, the method comprising: forming one or more openings in the planarized oxide layer disposed on a semi-insulated or conductive region and exposed to each planarized conductivity Filling one or more openings at approximately the same level as adjacent surfaces of the oxide layer to form a plug. The method of claim 1, wherein forming the one or more openings comprises etching the openings to be of different depths. 3. The method of claim 2, wherein forming at least one opening comprises forming at least one opening of the same diameter. The method of claim 1, wherein the filling comprises providing a layer of material on which the conductive material is deposited on the side of the one or more openings and depositing the conductive material to fill the one or more openings so that the conductive material is (a) Selectively depositing a layer of material on the side of the one or more openings and (b) a region exposed by the one or more openings. 5. The method of claim 4, wherein providing a silicon layer comprises chemically depositing silicon and selectively etching the deposited silicon to leave only silicon on the side of the one or more openings. The method of claim 1, wherein forming the one or more openings comprises etching the first one or more openings of the first selection depth that are deeper than the second selection depth associated with the second one or more openings to be successively formed. Wherein the filling step comprises depositing a conductive material to partially fill the first one or more openings to a level substantially equal to the second selection depth of the second one or more openings. How to. 7. The method of claim 6, wherein forming one or more openings comprises forming a second one or more openings of a second predetermined depth, and wherein filling is the first one or more openings that are partially filled. And depositing a conductive material, tungsten, to completely fill the second one or more openings. The method of claim 1, wherein the filling step provides a blanket of material onto which the conductive material is deposited, deposits the conductive material to fill one or more openings and a surface adjacent to the opening, the top of the one or more openings. Etching the deposited conductive material. 10. The method of claim 8, wherein providing a blanket layer of material comprises providing a blanket layer of refractory metal silicide. 10. The method of claim 8, wherein providing a blanket layer of material comprises providing a blanket layer consisting of silicon, titanium nitride, titanium, tungsten disulfide, titanium tungsten alloy, or tungsten nitride. . The method of claim 8, wherein providing a blanket layer of material comprises chemically depositing the material. The method of claim 1, wherein the filling step comprises providing a diffusion barrier layer on at least a bottom of the one or more openings, chemically depositing silicon to fill the one or more openings and the surface adjacent to the opening, Dope silicon, and etching the silicon deposited on top of the one or more openings. 13. The method of claim 12, wherein providing a diffusion barrier layer comprises providing a diffusion barrier layer comprised of refractory metal silicate. 13. The method of claim 12, wherein providing a diffusion barrier layer comprises providing a diffusion barrier layer comprised of titanium, titanium tungsten, titanium nitride, or tungsten nitride. 13. The method of claim 12, wherein providing a diffusion barrier layer comprises chemically depositing tungsten to form a layer of tungsten deposited below one or more openings. The method of claim 1, wherein the bottom of the one or more openings is made of metal, and the filling step chemically deposits silicon to fill the one or more openings and the surface adjacent the openings and dope the deposited silicon. And etching the silicon deposited on top of the one or more openings. A method for filling a contact or via opening in an integrated circuit with a conductive plug, the method comprising: forming one or more openings of the same diameter and at least one depth disposed on and exposed on a semi-insulating or conductive region in a planarized oxide layer And at least one filling with a conductive material at approximately the same level as adjacent surfaces of the oxide layer to form respective planarized conductive plugs. A method for filling a contact or via opening in an integrated circuit with a conductive plug, the method comprising: planarizing an oxide layer of a first one or more openings of a first predetermined depth disposed and exposed on respective associated semi-insulated or conductive regions; A second selected depth of the second selected depth that is formed within and partially fills the first one or more openings with the conductive material to a level corresponding to the second selected depth, each of which is disposed and exposed on an associated semi-insulating or conductive region, respectively. Forming at least one opening in the planarized oxide layer and filling the first and second at least one opening at approximately the same level to form respective planarized plugs in the opening. How to feature. 19. The method of claim 18, wherein forming the first one or more openings comprises forming openings of different diameters. 19. The method of claim 18, wherein forming the second one or more openings comprises forming openings of different diameters. 19. The method of claim 18, wherein partially filling the first one or more openings comprises depositing a material that is selectively deposited on each associated semi-insulating or conductive region. 22. The method of claim 21, wherein depositing the material comprises chemically depositing tungsten. 19. The method of claim 18, wherein filling the first and second one or more openings deposits a material that is selectively deposited on the semi-insulating or conductive regions respectively exposed by the second one or more openings. Method comprising a. The method of claim 23, wherein depositing the material comprises chemically depositing tungsten.

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